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* implement TII::insertNoopChris Lattner2006-03-051-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
* Compile this:Chris Lattner2006-03-011-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | void foo(float a, int *b) { *b = a; } to this: _foo: fctiwz f0, f1 stfiwx f0, 0, r4 blr instead of this: _foo: fctiwz f0, f1 stfd f0, -8(r1) lwz r2, -4(r1) stw r2, 0(r4) blr This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the right thing for GCC bugzilla 26505. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
* kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBCNate Begeman2006-02-171-8/+14
| | | | | | | | and SUBE nodes that actually expose what's going on and allow for significant simplifications in the targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/Nate Begeman2006-02-121-2/+4
| | | | | | | PowerPC/and-imm.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26136 91177308-0d34-0410-b5e6-96231b3b80d8
* PHI and INLINEASM are now built-in instructions provided by Target.tdChris Lattner2006-01-271-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
* ahem :)Chris Lattner2006-01-121-1/+1
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* Add bswap, rotl, and rotr nodesNate Begeman2006-01-111-3/+6
| | | | | | | | | | Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25222 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a comment that no longer applies.Nate Begeman2006-01-101-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25167 91177308-0d34-0410-b5e6-96231b3b80d8
* add ret void support backChris Lattner2006-01-091-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25164 91177308-0d34-0410-b5e6-96231b3b80d8
* New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replaceEvan Cheng2006-01-091-9/+5
| | | | | | | hasInFlag, hasOutFlag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25155 91177308-0d34-0410-b5e6-96231b3b80d8
* Added initial support for DEBUG_LABEL allowing debug specific labels to beJim Laskey2006-01-051-4/+7
| | | | | | | inserted in the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25104 91177308-0d34-0410-b5e6-96231b3b80d8
* Add unique id to debug location for debug label use (work in progress.)Jim Laskey2006-01-041-3/+4
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* Add support for generating v4i32 altivec codeNate Begeman2005-12-301-2/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25046 91177308-0d34-0410-b5e6-96231b3b80d8
* Added field noResults to Instruction.Evan Cheng2005-12-261-9/+10
| | | | | | | | | | | | | Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by separating results from inputs, e.g. (res R32:$dst), (ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding 'let noResults = 1' is the workaround to tell tblgen that the instruction does not produces a result. It works for now since tblgen does not support instructions which produce multiple results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
* * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.Evan Cheng2005-12-231-3/+6
| | | | | | | | | * Added a pseudo instruction (for each target) that represent "return void". This is a workaround for lack of optional flag operand (return void is not lowered so it does not have a flag operand.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24997 91177308-0d34-0410-b5e6-96231b3b80d8
* Flip the meaning of FPContractions to reflect Requires<[]> change.Evan Cheng2005-12-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24884 91177308-0d34-0410-b5e6-96231b3b80d8
* Pattern-match return. Includes gross hack!Nate Begeman2005-12-201-3/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24874 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert load/store over to being pattern matchedNate Begeman2005-12-191-77/+117
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24871 91177308-0d34-0410-b5e6-96231b3b80d8
* Added source file/line correspondence for dwarf (PowerPC only at this point.)Jim Laskey2005-12-161-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24748 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a second vector type to the VRRC register class, and fix some patternsNate Begeman2005-12-161-3/+3
| | | | | | | so that tablegen can infer all types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24746 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new predicate support that Evan Cheng added to remove some codeNate Begeman2005-12-141-10/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | from the DAGToDAG cpp file. This adds pattern support for vector and scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and does the right thing in the presence of -disable-excess-fp-precision. Allows us to match: void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = mul <4 x float> %tmp1, %tmp1 %tmp3 = add <4 x float> %tmp2, %tmp1 store <4 x float> %tmp3, <4 x float> *%a ret void } As: _foo: li r2, 0 lvx v0, r2, r3 vmaddfp v0, v0, v0, v0 stvx v0, r2, r3 blr Or, with llc -disable-excess-fp-precision, _foo: li r2, 0 lvx v0, r2, r3 vxor v1, v1, v1 vmaddfp v1, v0, v0, v1 vaddfp v0, v1, v0 stvx v0, r2, r3 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
* Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS.Evan Cheng2005-12-141-4/+11
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* Add support for fmul node of type v4f32.Nate Begeman2005-12-141-0/+13
| | | | | | | | | | | | | | | | | | | | | | | void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = mul <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float> *%a ret void } Is selected to: _foo: li r2, 0 lvx v0, r2, r3 vxor v1, v1, v1 vmaddfp v0, v0, v0, v1 stvx v0, r2, r3 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24701 91177308-0d34-0410-b5e6-96231b3b80d8
* Prepare support for AltiVec multiply, divide, and sqrt.Nate Begeman2005-12-131-2/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24700 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove type casts that are no longer neededChris Lattner2005-12-111-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24661 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for TargetConstantPool nodes to the dag isel emitter, and useNate Begeman2005-12-101-1/+4
| | | | | | | | them in the PPC backend, to simplify some logic out of Select and SelectAddr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24657 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support patterns to many load and store instructions which willNate Begeman2005-12-091-47/+93
| | | | | | | hopefully use patterns in the near future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24651 91177308-0d34-0410-b5e6-96231b3b80d8
* Use new PPC-specific nodes to represent shifts which require the 6-bitChris Lattner2005-12-061-3/+22
| | | | | | | | | | amount handling that PPC provides. These are generated by the lowering code and prevents the dag combiner from assuming (rightfully) that the shifts don't only look at 5 bits. This fixes a miscompilation of crafty with the new front-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24615 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some explicit type casts so that tblgen knows the type of the shiftChris Lattner2005-12-051-5/+5
| | | | | | | amount, which is not necessarily the same as the type being shifted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24594 91177308-0d34-0410-b5e6-96231b3b80d8
* Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgenChris Lattner2005-12-041-3/+12
| | | | | | | improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24591 91177308-0d34-0410-b5e6-96231b3b80d8
* Finish moving uncond br over to .td file, remove from .cpp file.Chris Lattner2005-12-041-1/+1
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* Define BR in the .td file now that Evan made tblgen smarter.Chris Lattner2005-12-041-4/+8
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* Represent the encoding of the SPR instructions as they actually are, soNate Begeman2005-11-291-6/+8
| | | | | | | | that we can use the correct SPR numbers in the InstrInfo.td file. This is necessary to support VRsave. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24521 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the remainder of the AltiVec 4 x float instructions. FurtherNate Begeman2005-11-291-14/+47
| | | | | | | | enhancements will be necessary to teach the code generator that since there is no fmul, it will have to do vmaddfp, adding +0.0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24516 91177308-0d34-0410-b5e6-96231b3b80d8
* Small tweaks noticed while on the plane.Nate Begeman2005-11-261-4/+3
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* Some first bits of AltiVec stuff: Instruction Formats, Encodings, andNate Begeman2005-11-231-0/+49
| | | | | | | | | | | Registers. Apologies to Jim if the scheduling info so far isn't accurate. There's a few more things like VRsave support that need to be finished up in my local tree before I can commit code that Does The Right Thing for turning 4 x float into the various altivec packed float instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8
* disentangle call operands from branch operands a bitChris Lattner2005-11-171-1/+4
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* Generate LA and ADDIS when possible.Chris Lattner2005-11-171-4/+6
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* Add an initial hack at legalizing GlobalAddress into the appropriate nodesChris Lattner2005-11-171-0/+8
| | | | | | | | | | | | | | | | | on Darwin to remove smarts from the isel. This is currently disabled by default (uncomment setOperationAction(ISD::GlobalAddress to enable it). tblgen needs to become smarter about tglobaladdr nodes and bigger patterns needed to be added to the .td file. However, we can currently emit stuff like this: :) li r2, lo16(L_x$non_lazy_ptr) lis r3, ha16(L_x$non_lazy_ptr) lwzx r2, r3, r2 The obvious improvements will follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24390 91177308-0d34-0410-b5e6-96231b3b80d8
* LI could theoretically be used for the lo-part of a global address, just likeChris Lattner2005-11-171-1/+1
| | | | | | | lis can be used for the high part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24388 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch to clean up function call pseudos and support the BLA instruction,Nate Begeman2005-11-161-7/+6
| | | | | | | | which branches to an absolute address. This is required to support objc direct dispatch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24370 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for branch on ordered/unordered.Chris Lattner2005-10-281-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24067 91177308-0d34-0410-b5e6-96231b3b80d8
* autogen undefChris Lattner2005-10-251-3/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23991 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow pseudos to have patterns, no functionality changeChris Lattner2005-10-251-11/+11
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* Autogen fselChris Lattner2005-10-251-2/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23987 91177308-0d34-0410-b5e6-96231b3b80d8
* Autogen a few new ppc-specific nodesChris Lattner2005-10-251-3/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23985 91177308-0d34-0410-b5e6-96231b3b80d8
* Instead of aborting if not a case we can handle specially, break out andChris Lattner2005-10-211-1/+0
| | | | | | | | | let the generic code handle it. This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc. also, reindent this code git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23874 91177308-0d34-0410-b5e6-96231b3b80d8
* Match rotate. This does actually match the rotates in an rc5 cipher, but INate Begeman2005-10-211-0/+3
| | | | | | | haven't seen it fire on our testsuite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23863 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some more patterns for i64 on ppcNate Begeman2005-10-201-6/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23842 91177308-0d34-0410-b5e6-96231b3b80d8
* Added InstrSchedClass to each of the PowerPC Instructions.Jim Laskey2005-10-191-172/+173
| | | | | | | | Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
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