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path: root/lib/Target/R600/SIISelLowering.cpp
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* R600/SI: Use VSrc_* register classes as the default classes for typesTom Stellard2013-08-061-21/+7
* R600/SI: Add more special cases for opcodes to ensureSRegLimit()Tom Stellard2013-08-061-32/+56
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-011-0/+15
* R600: Improve support for < 32-bit loadsTom Stellard2013-07-231-2/+2
* R600/SI: Fix crash with VSELECTTom Stellard2013-07-181-1/+10
* R600/SI: Add support for 64-bit loadsTom Stellard2013-07-151-0/+2
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-121-0/+15
* R600/SI: Add initial double precision support for SITom Stellard2013-07-121-0/+1
* R600/SI: Initial local memory supportMichel Danzer2013-07-101-0/+5
* R600: Consolidate expansion of v2i32/v4i32 ops for EG/SIAaron Watry2013-06-251-30/+0
* R600/SI: Expand xor v2i32/v4i32Aaron Watry2013-06-251-0/+3
* R600/SI: Expand urem of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EGAaron Watry2013-06-251-0/+3
* R600/SI: Expand ashr of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+2
* R600/SI: Expand srl of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+2
* R600/SI: Expand shl of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand or of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand mul of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand and of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Report unaligned memory accesses as legal for > 32-bit typesTom Stellard2013-06-251-0/+12
* R600/SI: Expand sub for v2i32 and v4i32 for SITom Stellard2013-06-201-0/+3
* R600/SI: Expand add for v2i32 and v4i32Tom Stellard2013-06-201-0/+2
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-071-1/+0
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-3/+10
* R600: Replace predicate loop with predicate functionTom Stellard2013-06-051-11/+13
* R600/SI: Add support for work item and work group intrinsicsTom Stellard2013-06-031-13/+81
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-031-2/+26
* R600/SI: Custom lower i64 sign_extendTom Stellard2013-06-031-0/+18
* R600/SI: Adjust some instructions' out register class after ISelTom Stellard2013-06-031-0/+51
* R600/SI: Handle REG_SEQUENCE in fitsRegClass()Tom Stellard2013-06-031-3/+13
* R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOpera...Tom Stellard2013-06-031-0/+16
* R600/SI: Rework MUBUF store instructionsTom Stellard2013-06-031-30/+30
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-9/+8
* Move passes from namespace llvm into anonymous namespaces. Sort includes whil...Benjamin Kramer2013-05-231-2/+2
* R600: Hide symbols of implementation details.Benjamin Kramer2013-05-231-1/+1
* Attempt to fix the mingw32 bot.Rafael Espindola2013-05-221-4/+4
* R600/SI: Make fitsRegClass() operands constTom Stellard2013-05-201-1/+1
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-181-7/+7
* R600/SI: return undef instead of null for skipped argumentsChristian Konig2013-05-171-2/+2
* R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemaskTom Stellard2013-05-061-1/+1
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-191-1/+1
* R600/SI: dynamical figure out the reg class of MIMGChristian Konig2013-04-101-2/+37
* R600/SI: adjust writemask to only the used componentsChristian Konig2013-04-101-2/+79
* R600/SI: Add support for buffer stores v2Tom Stellard2013-04-051-0/+32
* R600/SI: Avoid generating S_MOVs with 64-bit immediates v2Tom Stellard2013-04-051-2/+5
* R600/SI: add cummuting of rev instructionsChristian Konig2013-03-271-8/+14
* R600/SI: improve post ISel foldingChristian Konig2013-03-261-31/+43
* R600/SI: switch back to RegPressure schedulingChristian Konig2013-03-261-1/+1
* R600/SI: replace WQM intrinsicChristian Konig2013-03-261-13/+0
* R600/SI: implement indirect adressing for SIChristian Konig2013-03-181-0/+5
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