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* Allow subtarget selection of the default MachineScheduler and document the in...Andrew Trick2013-09-202-8/+14
* R600: Move clamp handling code to R600IselLowering.cppVincent Lejeune2013-09-122-33/+17
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-122-109/+59
* R600: Move fabs/fneg/sel folding logic into PostProcessIselVincent Lejeune2013-09-123-245/+197
* R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedbackTom Stellard2013-09-127-5/+113
* R600: Don't use trans slot for instructions that read LDS source registersTom Stellard2013-09-125-1/+34
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-3/+5
* R600: Add support for LDS atomic subtractAaron Watry2013-09-063-0/+13
* R600: Coding styleTom Stellard2013-09-051-6/+4
* R600: Fix i64 to i32 trunc on SIMatt Arsenault2013-09-051-0/+1
* R600: Add support for local memory atomic addTom Stellard2013-09-057-14/+78
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-052-15/+6
* R600: Fix incorrect LDS size calculationTom Stellard2013-09-052-4/+14
* R600/SI: Don't emit S_WQM_B64 instruction for compute shadersTom Stellard2013-09-051-1/+2
* R600: Fix segfault in R600TextureIntrinsicReplacerTom Stellard2013-09-051-0/+3
* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-041-0/+2
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-044-19/+60
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-09-044-23/+19
* Add llvm namespace to llvm::next.Michael Gottesman2013-09-041-2/+2
* Use llvm::next() instead of incrementing begin iterators of std::vector.Michael Gottesman2013-09-041-2/+2
* Mark an unreachable code path with llvm_unreachable. Pacifies GCC.Benjamin Kramer2013-08-311-0/+1
* R600: Add support for vector local memory loadsTom Stellard2013-08-264-0/+50
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-264-16/+59
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-268-15/+60
* R600: Add support for v4i32 and v2i32 local storesTom Stellard2013-08-263-59/+107
* SelectionDAG: Use correct pointer size when lowering function arguments v2Tom Stellard2013-08-264-7/+12
* R600/SI: Fix another case of illegal VGPR to SGPR copyTom Stellard2013-08-221-1/+1
* R600: Remove unnecessary castsTom Stellard2013-08-211-8/+6
* Remove unused stdio.h includesDmitri Gribenko2013-08-183-3/+0
* R600: Fix possible use of an uninitialized variableTom Stellard2013-08-171-0/+1
* R600: Expand vector FRINT opsTom Stellard2013-08-161-0/+1
* R600: Expand vector FFLOOR opsTom Stellard2013-08-161-0/+1
* R600: Expand vector float operations for both SI and R600Tom Stellard2013-08-162-13/+18
* R600/SI: Add pattern for xor of i1Michel Danzer2013-08-161-1/+3
* R600/SI: Fix broken encoding of DS_WRITE_B32Michel Danzer2013-08-165-9/+23
* R600: Allocate memoperand in the MachienFunction so it doesn't leak.Benjamin Kramer2013-08-161-3/+4
* Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions"Tom Stellard2013-08-163-8/+10
* R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructionsTom Stellard2013-08-163-10/+8
* R600: Add support for global vector loads with element types less than 32-bitsTom Stellard2013-08-161-0/+13
* R600: Add support for global vector stores with elements less than 32-bitsTom Stellard2013-08-163-1/+72
* R600: Add support for i16 and i8 global storesTom Stellard2013-08-168-27/+106
* R600: Add support for v4i32 stores on CaymanTom Stellard2013-08-161-0/+1
* R600: Enable folding of inline literals into REQ_SEQUENCE instructionsTom Stellard2013-08-162-17/+23
* R600: Add IsExport bit to TableGen instruction definitionsTom Stellard2013-08-166-10/+16
* R600: Change the RAT instruction assembly names so they match the docsTom Stellard2013-08-162-32/+35
* Fix spellingMatt Arsenault2013-08-151-7/+7
* Tentative fix for global-buffer-overflow caused by r188426. Found by AddressS...Alexey Samsonov2013-08-151-1/+4
* R600/SI: Improve legalization of vector operationsTom Stellard2013-08-144-5/+56
* R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsicsTom Stellard2013-08-144-4/+18
* R600/SI: Convert v16i8 resource descriptors to i128Tom Stellard2013-08-1412-44/+280