aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/X86/X86Schedule.td
Commit message (Expand)AuthorAgeFilesLines
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-6/+15
* Update to LLVM 3.5a.Stephen Hines2014-04-241-2/+37
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-8/+40
* Fix IMULX machine model. Multiple def operands require multiple SchedWrites.Andrew Trick2013-06-211-0/+1
* Update machine models. Specify buffer sizes for OOO processors.Andrew Trick2013-06-151-3/+4
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-5/+0
* Corrected Atom latencies for SSE SQRT instructions.Preston Gurd2013-05-071-4/+8
* Add the X86 FMAs to the scheduling model.Nadav Rotem2013-03-281-0/+4
* Add the Haswell machine model.Nadav Rotem2013-03-281-0/+1
* Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen2013-03-261-0/+1
* Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen2013-03-251-1/+0
* Add a WriteMicrocoded for ancient microcoded instructions.Jakob Stoklund Olesen2013-03-211-0/+3
* Add a catch-all WriteSystem SchedWrite type.Jakob Stoklund Olesen2013-03-201-0/+3
* Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-0/+4
* Define more SchedWrites for annotating X86 instructions.Jakob Stoklund Olesen2013-03-161-11/+57
* Prepare for adding InstrSchedModel annotations to X86 instructions.Jakob Stoklund Olesen2013-03-141-0/+26
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-091-0/+5
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-9/+7
* X86 itinerary properties.Andrew Trick2012-06-051-1/+23
* whitespaceAndrew Trick2012-06-051-4/+1
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-111-0/+36
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-101-0/+64
* Adds Intel Atom scheduling latencies to X86InstrSystem.td.Preston Gurd2012-05-041-0/+53
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-021-0/+38
* This patch adds X86 instruction itineraries for non-pseudo opcodes inPreston Gurd2012-03-191-0/+11
* Intel Atom instruction itineraries for mov sign extension and mov zero extens...Andrew Trick2012-02-291-0/+11
* This patch adds instruction latencies for the SSE instructionsPreston Gurd2012-02-271-0/+136
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-0/+115