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* The new t2LEApcrel* pseudo instructions need the size specified.Jim Grosbach2010-12-152-5/+13
* Implement cleanups suggested by Daniel.Owen Anderson2010-12-152-11/+15
* Fix build.Jakob Stoklund Olesen2010-12-151-1/+1
* Detect and enumerate bypass loops.Jakob Stoklund Olesen2010-12-152-0/+39
* Separate SplitAnalysis::getSplitLoops().Jakob Stoklund Olesen2010-12-152-7/+14
* Move Sub simplifications and additional Add simplifications out ofDuncan Sands2010-12-152-38/+71
* If we detect that the instruction we are simplifying is unreachable, arrange forDuncan Sands2010-12-151-3/+3
* Teach jump threading to "look through" a select when the branch direction of ...Frits van Bommel2010-12-151-0/+34
* Add fixups for Thumb LDR/STR instructions.Bill Wendling2010-12-153-3/+20
* Relax alignment fragments.Rafael Espindola2010-12-151-29/+26
* Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments.Rafael Espindola2010-12-151-2/+5
* add another overflow idiomChris Lattner2010-12-151-0/+8
* add a note about overflow idiom recognition.Chris Lattner2010-12-151-1/+19
* Generalize an assert.Rafael Espindola2010-12-151-1/+2
* add a shift/imul missed optimizationChris Lattner2010-12-151-0/+45
* add a note about a SPEC hack that gcc mainline does.Chris Lattner2010-12-151-0/+23
* take care of some todos, transforming [us]mul_lohi into Chris Lattner2010-12-151-2/+46
* when transforming a MULHS into a wider MUL, there is no need to SRA theChris Lattner2010-12-151-1/+1
* make qsort predicate more conformant by returning 0 for equal values.Chris Lattner2010-12-151-1/+5
* Reapply r121808 now that the missing patterns have been supplied.Bill Wendling2010-12-151-16/+21
* Add some missing patterns now that tLDRB and tLDRH are split into reg andBill Wendling2010-12-151-2/+12
* Fix PR8790, another instance where unreachable code can cause instruction sim...Owen Anderson2010-12-151-1/+6
* Cleanup trailing whitespace.Owen Anderson2010-12-151-27/+27
* Revert r121808 until I can fix the build.Bill Wendling2010-12-151-21/+16
* thumb adr fixup needs alignment just like the t2 version.Jim Grosbach2010-12-141-1/+2
* Comments and cleaning.Bill Wendling2010-12-141-6/+4
* Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. InBill Wendling2010-12-141-16/+21
* Simplify RegAllocGreedy's use of register aliases.Jakob Stoklund Olesen2010-12-141-17/+4
* Simplify CCState's use of register aliases.Jakob Stoklund Olesen2010-12-141-5/+3
* Simplify AggressiveAntiDepBreaker's use of register aliases.Jakob Stoklund Olesen2010-12-141-31/+14
* Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet.Jakob Stoklund Olesen2010-12-141-14/+4
* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-146-21/+50
* Fix comment.Bill Wendling2010-12-141-1/+1
* Multiclassify the LDR/STR encoding patterns. The only functionality differenceBill Wendling2010-12-141-69/+69
* Fix a minor bug in two-address pass. It was missing a commute opportunity.Evan Cheng2010-12-141-1/+2
* trailing whitespaceJim Grosbach2010-12-141-4/+4
* Move debugging code entirely within DEBUG(). Silences an unused variableMatt Beaumont-Gay2010-12-141-8/+8
* Refactor a bit for legibility.Jim Grosbach2010-12-141-28/+27
* trailing whitespace.Jim Grosbach2010-12-141-4/+4
* Make sure to propagate the predicate operands for LEApcrel to ADR.Jim Grosbach2010-12-141-4/+4
* Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.Owen Anderson2010-12-141-1/+1
* Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew.Jakob Stoklund Olesen2010-12-143-5/+52
* Use TRI::printReg instead of AbstractRegisterDescription when printingJakob Stoklund Olesen2010-12-143-34/+13
* Add TargetRegisterInfo::printReg() to pretty-print registers.Jakob Stoklund Olesen2010-12-141-0/+8
* ARM Fixups relative to thumb functions need to have the low bit of the valueJim Grosbach2010-12-142-0/+14
* Q.seenAllInterferences() must be called after Q.collectInterferingVRegs().Jakob Stoklund Olesen2010-12-141-2/+4
* MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.Daniel Dunbar2010-12-141-1/+1
* Trailing whitespaceJim Grosbach2010-12-141-6/+6
* Use the integer scheduling intrinsic for integer loads and stores.Bill Wendling2010-12-141-6/+6
* - Insert new instructions before DomBlock's terminator,Chris Lattner2010-12-141-7/+16
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