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* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-098-5/+411
| | | | Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-2386-105/+10606
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-0222-7/+751
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-2116-67/+172
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-2951-1483/+2418
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-2442-0/+11698
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Merging r195936:Bill Wendling2013-12-011-0/+17
| | | | | | | | | | | ------------------------------------------------------------------------ r195936 | kevinqin | 2013-11-28 17:29:16 -0800 (Thu, 28 Nov 2013) | 1 line [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196028 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195903:Bill Wendling2013-12-011-1/+3
| | | | | | | | | | | | ------------------------------------------------------------------------ r195903 | haoliu | 2013-11-27 17:07:45 -0800 (Wed, 27 Nov 2013) | 2 lines AArch64: Fix a bug about disassembling post-index load single element to 4 vectors ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196025 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195803:Bill Wendling2013-12-011-0/+8
| | | | | | | | | | | ------------------------------------------------------------------------ r195803 | mcrosier | 2013-11-26 17:45:58 -0800 (Tue, 26 Nov 2013) | 1 line [AArch64] Add support for NEON scalar floating-point absolute difference. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195994 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195788:Bill Wendling2013-12-011-0/+99
| | | | | | | | | | | | ------------------------------------------------------------------------ r195788 | mcrosier | 2013-11-26 14:17:37 -0800 (Tue, 26 Nov 2013) | 2 lines [AArch64] Add support for NEON scalar floating-point to integer convert instructions. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195993 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195591:Bill Wendling2013-11-251-7/+7
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195591 | haoliu | 2013-11-24 17:53:26 -0800 (Sun, 24 Nov 2013) | 5 lines Fixed a bug about disassembling AArch64 post-index load/store single element instructions. ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble will be disassembled into the same instruction st1 {v0b}[0], [x0], x0. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195619 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-191-0/+84
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-141-1/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add the general form of BCRRichard Sandiford2013-11-131-0/+45
| | | | | | | At the moment this is just the MC support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS trap instruction with immediate operands.Zoran Jovanovic2013-11-132-0/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalarChad Rosier2013-11-121-0/+213
| | | | | | | | copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Add support for MVFR2 which is new in ARMv8Artyom Skrobov2013-11-112-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point ↵Chad Rosier2013-11-111-0/+16
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-082-0/+202
| | | | | | ARMv8 (Thumb encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-0/+167
| | | | | | ARMv8 (ARM encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194262 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-0/+35
| | | | | | ARMv8 (ARM encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS trap instructions 1.Zoran Jovanovic2013-11-072-0/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 Neon instruction set Perm.Jiangning Liu2013-11-061-0/+107
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 Neon instruction set Bitwise Extract.Jiangning Liu2013-11-061-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 post-index vector load/store multiple N-element structure ↵Hao Liu2013-11-051-1/+72
| | | | | | | | | | | | | class SIMD(lselem-post). Including following 14 instructions: 4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS branch instructions.Zoran Jovanovic2013-11-042-0/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar fixed-point convert to floating-point ↵Chad Rosier2013-10-311-0/+16
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar shift immediate instructions.Chad Rosier2013-10-311-0/+162
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Make the use of FP instructions optional, but enabled by default.Amara Emerson2013-10-315-5/+5
| | | | | | | | This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] NEON instructions were erroneously decoded from certain invalid encodingsArtyom Skrobov2013-10-301-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193705 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point compare instructions.Chad Rosier2013-10-301-0/+80
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS jump instructionsZoran Jovanovic2013-10-292-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ARM hint ranges consistent, and add tests for these rangesArtyom Skrobov2013-10-231-2/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: provide diagnostics on more writeback LDM/STM instructionsTim Northover2013-10-221-0/+16
| | | | | | | | | | | | | | The set of circumstances where the writeback register is allowed to be in the list of registers is rather baroque, but I think this implements them all on the assembly parsing side. For disassembly, we still warn about an ARM-mode LDM even if the architecture revision is < v7 (the required architecture information isn't available). It's a silly instruction anyway, so hopefully no-one will mind. rdar://problem/15223374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-182-13/+8
| | | | | | | | Patch by Artyom Skrobov git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192972 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar extract narrow instructions.Chad Rosier2013-10-181-0/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar three register different instructionChad Rosier2013-10-171-0/+24
| | | | | | | | class. The instruction class includes the signed saturating doubling multiply-add long, signed saturating doubling multiply-subtract long, and the signed saturating doubling multiply long instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar negate instruction.Chad Rosier2013-10-161-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar absolute value instruction.Chad Rosier2013-10-161-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comment.Chad Rosier2013-10-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192806 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar signed saturating accumulated of unsignedChad Rosier2013-10-161-0/+24
| | | | | | value and unsigned saturating accumulate of signed value instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192800 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar signed saturating absolute value andChad Rosier2013-10-151-0/+24
| | | | | | scalar signed saturating negate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192733 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar integer compare instructions.Chad Rosier2013-10-141-0/+67
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembler support for SSE4.1 register/register form of PEXTRW. There ↵Craig Topper2013-10-141-0/+6
| | | | | | is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips: Disassemble sign-extended 64 bit immediates properly.Benjamin Kramer2013-10-111-0/+3
| | | | | | This doesn't change the meaning of the output, but makes look right. PR17539. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192483 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point reciprocal estimate,Chad Rosier2013-10-081-0/+24
| | | | | | reciprocal exponent, and reciprocal square root estimate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar signed/unsigned integer to floating-pointChad Rosier2013-10-081-0/+16
| | | | | | convert instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some instructions that existed to provide aliases to the assembler. ↵Craig Topper2013-10-081-0/+6
| | | | | | Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar arithmetic instructions:Chad Rosier2013-10-071-0/+40
| | | | | | SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add some disassembly tests for Thumb sevl/sevl.wJoey Gouly2013-10-071-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192106 91177308-0d34-0410-b5e6-96231b3b80d8
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