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* Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some ta...Evan Cheng2011-04-151-6/+12
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-155-10/+10
* Add an option to not print the alias of an instruction. It defaults to "printBill Wendling2011-04-131-0/+2
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+4
* TableGen: Keep the order of DECL_CONTEXT() for DeclNodes.td. RecordVector may...NAKAMURA Takumi2011-04-111-4/+7
* Only emit the AvailableFeatures variable if it's used.Bill Wendling2011-04-081-4/+7
* Replace the old algorithm that emitted the "print the alias for an instruction"Bill Wendling2011-04-071-146/+59
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-044-10/+31
* Use array_lengthofJoerg Sonnenberger2011-04-041-2/+3
* Change loops to derive the number of tables automaticallyJoerg Sonnenberger2011-04-041-2/+2
* tlbgen/MC: StringRef's to temporary objects considered harmful.Daniel Dunbar2011-04-011-3/+3
* Add annotations to tablegen-generated processor itineraries, or replace them ...Andrew Trick2011-04-012-16/+21
* whitespaceAndrew Trick2011-04-012-68/+68
* Use intrinsics for Neon vmull operations. Radar 9208957.Bob Wilson2011-03-312-27/+17
* ClangSAEmClangSACheckersEmitter, emit info about groups.Argyrios Kyrtzidis2011-03-301-64/+79
* Quiet a gcc warning about changed name lookup rulesMatt Beaumont-Gay2011-03-291-2/+2
* In ClangSACheckersEmitter:Argyrios Kyrtzidis2011-03-291-7/+61
* For ClangSACheckersEmitter, allow a package to belong to checker group, in wh...Argyrios Kyrtzidis2011-03-291-8/+28
* Extend Clang's TableGen emitter for attributes to support bool arguments.Douglas Gregor2011-03-261-0/+2
* delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ins...Johnny Chen2011-03-251-0/+5
* The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ...Johnny Chen2011-03-241-2/+2
* The ARM disassembler was confused with the 16-bit tSTMIA instruction.Johnny Chen2011-03-241-0/+5
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-241-0/+4
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder wa...Johnny Chen2011-03-241-0/+4
* Update the Clang attribute emitter to handle attributes of 'version'Douglas Gregor2011-03-231-0/+46
* Call static functions so that they aren't left unused.Bill Wendling2011-03-211-2/+4
* A WIP commit of the InstAlias printing cleanup. This code will soon replace theBill Wendling2011-03-211-19/+121
* Add the IAPrinter class.Bill Wendling2011-03-211-0/+97
* * Add classes that support the "feature" information.Bill Wendling2011-03-212-5/+120
* Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson2011-03-181-0/+1
* - Add "Bitcast" target instruction property for instructions which performEvan Cheng2011-03-154-9/+40
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-153-52/+250
* Ignore isCodeGenOnly instructions when generating diassembly tables.Owen Anderson2011-03-141-1/+2
* Trailing whitespace.Jim Grosbach2011-03-141-46/+46
* Correct small comment order typo.Francois Pichet2011-03-141-1/+1
* Remove no-longer-correct special case for disasm of ARM BL instructions.Jim Grosbach2011-03-121-5/+0
* Pseudo-ize the ARM 'B' instruction.Jim Grosbach2011-03-111-3/+0
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-111-8/+0
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-111-9/+0
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-111-3/+2
* Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach2011-03-111-14/+0
* ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach2011-03-111-6/+0
* Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach2011-03-111-10/+0
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-111-4/+1
* ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach2011-03-111-7/+0
* Add missing 'return on failure'. Previously we'd crash after emittingJim Grosbach2011-03-111-0/+1
* Teach TableGen to pre-calculate register enum values when creating theJim Grosbach2011-03-114-33/+36
* Make the register enum value part of the CodeGenRegister struct.Jim Grosbach2011-03-113-1/+8
* Trailing whitespace.Jim Grosbach2011-03-112-33/+33
* Trailing whitespace.Jim Grosbach2011-03-112-49/+49
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