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path: root/src/mesa/drivers/dri/i965/brw_defines.h
Commit message (Expand)AuthorAgeFilesLines
* i965/gen7: Use predicated rendering for indirect computeJordan Justen2016-02-171-0/+1
* i965: Add resolve option for lossless compressionTopi Pohjolainen2016-02-161-0/+1
* i965/fs: Plumb separate surfaces and samplers through from NIRJason Ekstrand2016-02-091-1/+3
* i965/fs: Add an enum for keeping track of texture instruciton sourcesJason Ekstrand2016-02-091-13/+27
* i965/fs: Implement support for extract_word.Matt Turner2016-02-011-0/+12
* i965: Don't set interleave or complete on TCS EOT message.Kenneth Graunke2015-12-281-0/+1
* i965: Relase input URB Handles on Gen7/7.5 when TCS threads finish.Kenneth Graunke2015-12-281-0/+2
* i965: Port tessellation evaluation shaders to vec4 mode.Kenneth Graunke2015-12-281-0/+4
* i965: Add tessellation control shaders.Kenneth Graunke2015-12-221-0/+8
* i965: Enable shared local memory for CS shared variablesJordan Justen2015-12-091-0/+2
* i965: Define and use REG_MASK macro to make masked MMIO writes slightly more ...Francisco Jerez2015-12-091-0/+6
* i965: Add defines for gather push constantsAbdiel Janulgue2015-12-071-0/+19
* i965: Add symbolic defines for some magic dataport surface indices.Francisco Jerez2015-11-261-0/+13
* i965: Add more MAX_*_URB_ENTRY_SIZE_BYTES #defines.Kenneth Graunke2015-11-171-0/+6
* i965: Introduce a MOV_INDIRECT opcode.Kenneth Graunke2015-11-141-0/+10
* i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.Kenneth Graunke2015-11-131-5/+2
* i965: Combine register file field.Matt Turner2015-11-131-0/+11
* i965: Add and use enum brw_reg_file.Matt Turner2015-11-131-4/+6
* i965: Fill out instruction list.Matt Turner2015-11-121-7/+31
* i965: Map GL_PATCHES to 3DPRIM_PATCHLIST_n.Kenneth Graunke2015-11-111-0/+2
* i965/fs/skl+: Use ld2dms_w instead of ld2dmsNeil Roberts2015-11-051-0/+3
* i965: Implement ARB_shader_stencil_export (gen9+)Ben Widawsky2015-10-211-0/+2
* i965/fs: Enumerate logical fb writes argumentsBen Widawsky2015-10-211-9/+13
* i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode.Kenneth Graunke2015-10-211-0/+9
* i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes.Kenneth Graunke2015-10-211-0/+3
* i965: (trivial) rename computes stencil to gen9Ben Widawsky2015-10-211-1/+1
* i965: Correct the comment about fb write payloadBen Widawsky2015-10-211-2/+2
* i965: Implement "Static Vertex Count" geometry shader optimization.Kenneth Graunke2015-09-261-0/+5
* i965/fs: Implement FS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsalvez2015-09-251-0/+1
* i965/vec4: Implement VS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsalvez2015-09-251-0/+3
* i965/cs: Implement DispatchComputeIndirect supportJordan Justen2015-09-241-0/+2
* i965: Add defines for tessellation stagesChris Forbes2015-09-221-0/+72
* i965/cs: Enable barrier in MEDIA_INTERFACE_DESCRIPTORJordan Justen2015-09-101-0/+2
* i965: add support for textureSamples functionIlia Mirkin2015-09-101-0/+2
* i965: Mark topologies with adjacency information as G45+.Kenneth Graunke2015-09-081-4/+4
* i965: Fix value of _3DPRIM_TRIFAN_NOSTIPPLE.Kenneth Graunke2015-09-081-1/+1
* i965: Add defines for all new Gen7/8 URB opcodesChris Forbes2015-09-081-1/+7
* i965/gen9: Annotate input coverage mask changeBen Widawsky2015-09-031-0/+16
* i965/cs: Setup push constant data for uniformsJordan Justen2015-09-021-0/+6
* i965/chv|skl: Apply sampler bypass w/aBen Widawsky2015-08-311-0/+1
* i965/surface_formats: add support for 2D ASTC surface formatsNanley Chery2015-08-261-0/+32
* i965/gen7-8: Set up early depth/stencil control appropriately for image load/...Francisco Jerez2015-08-111-0/+3
* i965/gen7-8: Poke the 3DSTATE UAV access enable bits.Francisco Jerez2015-08-111-0/+4
* i965: Define virtual instruction to calculate the high 32 bits of a multiply.Francisco Jerez2015-08-061-0/+5
* i965/fs: Define logical typed and untyped surface opcodes.Francisco Jerez2015-07-291-0/+20
* i965/fs: Define logical texture sampling opcodes.Francisco Jerez2015-07-291-0/+31
* i965/fs: Remove the FS_OPCODE_SET_OMASK pseudo-opcode.Francisco Jerez2015-07-291-1/+0
* i965/fs: Define logical framebuffer write opcode.Francisco Jerez2015-07-291-0/+15
* i965: Define HW-binding table and resource streamer control opcodesAbdiel Janulgue2015-07-181-0/+30
* i965/gen9: Use custom MOCS entries set up by the kernel.Francisco Jerez2015-07-161-5/+6
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