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* i965: Refactor rb surface setup to allow caller to store offsetsTopi Pohjolainen2015-04-301-14/+14
| | | | | | | | | | | Notice that in gen7_wm_surface_state.c there is also indentation change in the surrounding code removing tabs. v2 (Matt): Fixed whitespace: tabs -> spaces Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/gen7: Factor out texture surface state set-up from ↵Francisco Jerez2015-04-271-54/+73
| | | | | | | gen7_update_texture_surface(). This moves most of the surface state set-up logic that can be shared between textures and shader images to a separate function.
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-141-1/+1
| | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Acked-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Marius Predut <marius.predut@intel.com>
* i965: Fix depth field setting in surface state for raw buffer on Gen7/8Zhenyu Wang2015-04-081-2/+5
| | | | | | | | | | On Gen7/8 for RAW surface format, the depth field (surf[3]) in surface state means [30:21] bits of number of entries which is different from other surface format which uses [26:21] bits field. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965: Make sure we always mark array surfaces as suchIago Toral Quiroga2015-04-061-1/+3
| | | | | | | | | | Even if they only have one slice, otherwise textureSize() won't produce correct results for the depth value. Fixes 10 dEQP tests in this category: dEQP-GLES3.functional.shaders.texture_functions.texturesize.sampler2darray* Reviewed-by: Mark Janes <mark.a.janes at intel.com>
* i965: Remove the create_raw_surface vtbl hook.Francisco Jerez2015-03-021-19/+0
| | | | | | | | It's a wrapper around emit_buffer_surface_state with format=RAW, pitch=1, rw=true and the remaining arguments ordered differently. There's no point in having a separate vtbl pointer for that. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
* i965: Generalize the update_null_renderbuffer_surface vtbl hook to ↵Francisco Jerez2015-02-101-14/+10
| | | | | | | | | | | | | non-renderbuffers. Null surfaces are going to be useful to have something to point unbound image units to, as the ARB_shader_image_load_store extension requires us to behave deterministically in cases where some shader tries to access an unbound image unit: Invalid stores and atomics are supposed to be discarded and invalid loads are supposed to return zero, which is precisely what the null surface does. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Fix integer border color on Haswell.Kenneth Graunke2015-02-091-0/+3
| | | | | | | | | +82 Piglits - 100% of border color tests now pass on Haswell. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Cc: mesa-stable@lists.freedesktop.org
* i965: Enable L3 caching of buffer surfaces.Francisco Jerez2015-01-311-3/+1
| | | | | | | | | | | | | | | And remove the mocs argument of the emit_buffer_surface_state vtbl hook. Its semantics vary greatly from one generation to another, so it kind of encourages the caller to pass 0 which is the only valid setting across generations. After this commit the hardware-specific code decides what the best cacheability settings are for buffer surfaces, just like we do for textures. This together with some additional changes coming is expected to improve performance of pull constants, buffer textures, atomic counters and image objects on Gen7 and up. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Apply the miptree offset to surface state for renderbuffersJason Ekstrand2015-01-221-1/+2
| | | | | | | | | Previously, we were completely ignoring the mt->offset field for renderbuffers. While it does have some alignment constraints, it is valid to use it. This patch adds the code to each of the 4 surface state setup functions to handle it. Reviewed-by: Neil Roberts <neil@linux.intel.com>
* i965: Micro-optimize swizzle_to_scs() and make it inlinable.Kenneth Graunke2015-01-041-22/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | brw_swizzle_to_scs has been showing up in my CPU profiling, which is rather silly - it's a tiny amount of code. It really should be inlined, and can easily be implemented with fewer instructions. The enum translation is as follows: SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE 0 1 2 3 4 5 4 5 6 7 0 1 SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE which is simply (swizzle + 4) & 7. Haswell needs extra textureGather workarounds to remap GREEN to BLUE, but Broadwell and later do not. This patch replicates swizzle_to_scs in gen7_wm_surface_state.c and gen8_surface_state.c, since the Gen8+ code can be simplified to a mere two instructions. Both copies can be marked static for easy inlining. v2: Put the commit message in the code as comments (requested by Jason Ekstrand). Also fix a typo. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
* i965: Change mipmap array_spacing_lod0 to array_layout (enum)Jordan Justen2014-08-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will want to setup gen6 separate stencil and hiz miptrees in a layout that is similar to array_spacing_lod0. This is needed because gen6 hiz and stencil only support a single mip-level. In both use cases (gen7+ LOD0 spacing & gen6 separate stencil/hiz), the array slices will be packed at each LOD without reserving extra space for LODs within each array slice. So, we generalize the name of this field and add comments to indicate the old and new uses. Motivation for the gen6 change comes from the PRM: PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK] to [DevSNB]: "The separate stencil buffer does not support mip mapping, thus the storage for LODs other than LOD 0 is not needed." PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer "[DevSNB]: The hierarchical depth buffer does not support the LOD field, it is assumed by hardware to be zero. A separate hierarachical depth buffer is required for each LOD used, and the corresponding buffer’s state delivered to hardware each time a new depth buffer state with modified LOD is delivered." v2: * Rename array_spacing_lod0 to non_mip_arrays v3: * Instead, replace array_spacing_lod0 with array_layout enum Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Add a comment about null renderbuffer surfaces and why they exist.Eric Anholt2014-07-021-0/+8
| | | | | | I noticed this when trying to find comments about pull constant buffers. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Use unreachable() instead of unconditional assert().Matt Turner2014-07-011-2/+1
| | | | Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Set the fast clear color value for texture surfacesNeil Roberts2014-06-121-1/+3
| | | | | | | | | | | | | | When a multisampled texture is used for sampling the fast clear color value needs to be programmed into the surface state. This was being left as all zeroes so if the surface was cleared to a value other than black then it wouldn't work properly. This doesn't matter for single-sample textures because in that case the MCS buffer is resolved before it is used as a texture source. https://bugs.freedesktop.org/show_bug.cgi?id=79729 Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
* i965/gen7 renderbuffer: Set depth size based on LOD0 for 3D texturesJordan Justen2014-05-131-1/+1
| | | | | | | | | | | | If blorp is disabled for color clears, then piglit's 'gl-3.2-layered-rendering-clear-color-all-types 3d mipmapped' will fail. Currently, gen8 fails similarly on this test because gen8 does not use blorp. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
* Revert "i965: Fix depth (array slices) computation for 1D_ARRAY render targets."Kenneth Graunke2014-05-091-2/+0
| | | | | | | | | | This reverts commit e6967270c75a5b669152127bb7a746d55f4407a6. Chris Forbes pointed out that this is broken for texture views which restrict the number of slices. He committed a better fix which makes this unnecessary. Cc: "10.2" <mesa-stable@lists.freedesktop.org>
* i965/Gen7: Set up layer constraints properly for renderbuffersChris Forbes2014-05-091-10/+7
| | | | | | | | | | | | | | | | There were a few problems here, which mostly just broke layered rendering into a view: - Render target view extent was always set to be == depth. This is benign for non-layered-rendering, but allows writes off the end of the render target for layered rendering, which ends badly. - Layered rendering did not honor the mt_layer setting, so would not properly handle MinLayer being set on a view. V2: Restore the MAX2() to account for zero depth/layer_count. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Fix depth (array slices) computation for 1D_ARRAY render targets.Kenneth Graunke2014-05-071-0/+2
| | | | | | | | | | | 1D array targets store the number of slices in the Height field. Fixes Piglit's spec/!OpenGL 3.2/layered-rendering/clear-color-all-types 1d_array single_level, at least when used with Meta clears. Cc: "10.2 10.1 10.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Drop use of intel_region from miptrees.Eric Anholt2014-05-011-16/+16
| | | | | | | | | | | | Note: region->width/height used to reflect the total_width/height padding of separate stencil, though mt->total_width didn't. region->width/height was being used in EGL images, where the padded value would have been the wrong one, so I converted them to use rb->Width/Height. v2: Drop debug printf that slipped in (caught by Ken) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
* i965: Adjust surface_state emission to account for view parametersChris Forbes2014-04-101-5/+14
| | | | | | | | | V4: Comment style, remove magic shift. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net>
* i965/wm: Use resolved miptree consistently in surface setupTopi Pohjolainen2014-03-051-5/+5
| | | | | | | | | | | | Most of the logic refers to the local variable 'mt' directly but a few cases use 'intelObj->mt' instead. These are the same for now but will be different once stencil miptree gets used. v2 (Ian): fixed also indentation in surrounding lines Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Use ffs() for sample counting in gen7_surface_msaa_bits().Kenneth Graunke2014-02-191-6/+4
| | | | | | | | | | | The enumerations are just log2(num_samples) shifted by 3, which we can easily compute via ffs(). This also makes it reusable for Broadwell, which has 2x MSAA. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* mesa: change gl_format to mesa_formatMark Mueller2014-01-271-1/+1
| | | | s/\bgl_format\b/mesa_format/g. Use better name for Mesa Formats enum
* i965: Use the new drm_intel_bo offset64 field.Kenneth Graunke2014-01-201-7/+7
| | | | | | | | | | | | | | | | | | | libdrm 2.4.52 introduces a new 'uint64_t offset64' field, intended to replace the old 'unsigned long offset' field. To preserve ABI, libdrm continues to store the presumed offset in both locations. On Broadwell, a 64-bit kernel may place BOs at "high" (> 4G) addresses. However, with a 32-bit userspace, the 'unsigned long offset' field will only be 32-bit, which is not large enough to hold this value. We need to use a proper uint64_t (like the kernel does). Technically, a lot of this code doesn't affect Broadwell, so we could leave it using the old field. But it makes sense to just switch to the new, properly typed field. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965/Gen7: Only emit cube face enables for cubes.Chris Forbes2014-01-191-2/+5
| | | | | | | | | This is not observed to actually fix anything, but the PRM says this field must be zero for other surface types. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Remove unused depth_mode parameter from translate_tex_format().Kenneth Graunke2013-12-291-1/+0
| | | | | | | | | | | | According to git blame, this hasn't been used in over two years: commit d2235b0f4681f75d562131d655a6d7b7033d2d8b Author: Eric Anholt <eric@anholt.net> Date: Thu Nov 17 17:01:58 2011 -0800 i965: Always handle GL_DEPTH_TEXTURE_MODE through the shader. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/Gen7: emit mcs info for multisample texturesChris Forbes2013-12-071-0/+5
| | | | | | | | Previously this was only done for render targets. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Make swizzle_to_scs non-static.Kenneth Graunke2013-11-161-6/+6
| | | | | | | | | | | | | | We'll need this for Broadwell code as well. Normally, when we make things public, we add the "brw" prefix. I'm not crazy about that in this case, since it deals with prog_instruction.h's SWIZZLE_XYZW values, rather than the BRW_SWIZZLE_XYZW enums. However, I can't think of a better name, and at least the comments and code make it clear. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965: Combine {brw,gen7}_update_texture_buffer_surface() functions.Kenneth Graunke2013-11-051-39/+1
| | | | | | | | Now that brw_update_texture_buffer_surface() uses the virtual emit_buffer_surface_state() function, it works for Gen7+ too. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965: Unvirtualize brw_create_constant_surface; delete Gen7+ variant.Kenneth Graunke2013-11-051-27/+0
| | | | | | | | | Now that brw_create_constant_surface uses a virtual function internally, it doesn't need to be virtual itself. We can delete the Gen7+ variant and simplify things. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965: Virtualize emit_buffer_surface_state().Kenneth Graunke2013-11-051-0/+1
| | | | | | | | | This entails adding "mocs" and "rw" parameters to the Gen4-5 version. I made it actually pay attention to the rw flag (even though it is always false), but mocs is always ignored. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965: Simplify the shader time code by using atomic counter helpers.Francisco Jerez2013-10-291-17/+0
| | | | Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965: Define vtbl method that initializes an untyped R/W surface.Francisco Jerez2013-10-291-5/+30
| | | | | | | | And add Gen7 implementation. v2: Fix off by one error in buffer size calculation. Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965: Try to avoid stalls on the GPU when doing glBufferSubData().Eric Anholt2013-10-231-1/+1
| | | | | | | | | | | | On DOTA2, framerate on dota2-de1.dem in windowed mode on my laptop improves by 7.69854% +/- 0.909163% (n=3). In a microbenchmark hitting this code path (wall time of piglit vbo-subdata-many), runtime decreases from 0.8 to 0.05 seconds. v2: Use out of range start/end instead of separate bool for the active flag (suggestion by Jordan), fix double-upload in the stalling path. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Add support for GL_ARB_texture_buffer_range.Eric Anholt2013-10-231-4/+10
| | | | | | | | | | | Supporting this extension turns out to simplify our code a bit over not supporting this extension, once the glBufferSubData() synchronization code lands. v2: Use 16 byte alignment like we do for uniform buffers, due to unaligned access penalties. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
* i965: Make a brw_stage_prog_data for storing the SURF_INDEX information.Eric Anholt2013-10-151-2/+5
| | | | | | | | | | | It would be nice to be able to pack our binding table so that programs that use 1 render target don't upload an extra BRW_MAX_DRAW_BUFFERS - 1 binding table entries. To do that, we need the compiled program to have information on where its surfaces go. v2: Rename size to size_bytes to be more explicit. Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965/hsw: Apply gather4 RG32F w/a using SCS instead of shader.Chris Forbes2013-10-031-6/+8
| | | | | | | | The new surface channel select bits allow us to avoid having to recompile the shader for this workaround. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Emit a second set of SURFACE_STATE for gather4 from textures.Chris Forbes2013-10-031-1/+5
| | | | | | | | | | | | | This allows us to use a different surface format for gather4, which is required for R32G32_FLOAT to work on Gen7. V4: - Only emit alternate surface state for shaders which will actually use it. - Pass a simple 'for_gather' flag rather than a function pointer. The callee can decide what w/a to apply. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Totally switch around how we handle nonzero baselevel-first_level.Eric Anholt2013-09-301-1/+3
| | | | | | | | | | | | | | | | | | | This has no effect currently, because intel_finalize_mipmap_tree() always makes mt->first_level == tObj->BaseLevel. The change I made before to handle it (b1080cfbdb0a084122fcd662cd27b4748c5598fd) got very close to working, but after fixing some unrelated bugs in the series, it still left tex-miplevel-selection producing errors when testing textureLod(). The problem is that for explicit LODs, the sampler's LOD clamping is ignored, and only the surface's MIP clamping is respected. So we need to use surface mip clamping, which applies on top of the sampler's mip clamping, so the sampler change gets backed out. Now actually tested with a non-regressing series producing a non-zero computed baselevel. Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
* i965: Always look up from the object's mt when setting up texturing state.Eric Anholt2013-09-301-2/+1
| | | | | | | | | | | We know that the object's mt is equal to the firstimage's mt because it's gone through intel_finalize_mipmap_tree(). Saves a lookup of firstimage on pre-gen7. v2: Merge in the warning fix that appeared later in the series (noted by Chad) Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
* i965/gen7.5: Fix missing Shader Channel Select entries on HaswellAbdiel Janulgue2013-09-211-0/+7
| | | | | | | | | | | Probably non-intentional, but the SURFACE_STATE setup refactoring for buffer surfaces had missed the scs bits when creating constant surface states. Fixes broken GLB 2.5 on Haswell where the knight's textures are missing Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Refactor Gen7+ SURFACE_STATE setup for buffer surfaces.Kenneth Graunke2013-09-191-86/+60
| | | | | | | | | | | | | | This was an embarassingly large amount of copy and pasted code, and it wasn't particularly simple code either. By factoring it out into a helper function, we consolidate the complexity. v2: Properly NULL-check bo. Caught by Eric Anholt. v3: Do the subtraction by 1 in gen7_emit_buffer_surface_state, rather than making callers do it. This makes the buffer_size parameter the actual size of the buffer. Suggested by Paul Berry. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Fix off by one errors in texture buffer size calculations.Kenneth Graunke2013-09-191-1/+1
| | | | | | | | | The value that's split into width/height/depth needs to be the size of the buffer minus one. This makes it consistent with the constant buffer and shader time SURFACE_STATE setup code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Use brw_stage_state for WM data as well.Kenneth Graunke2013-09-131-4/+4
| | | | | | | | This gets the VS, GS, and PS all using the same data structure. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965: Modify signature to update_texture_surface functions.Paul Berry2013-08-311-9/+7
| | | | | | | | | | | | Previously these functions would accept a pointer to the binding table and an index indicating which entry in the binding table should be updated. Now they merely take a pointer to the binding table entry to be updated. This will make it easier to generalize brw_texture_surfaces to support geometry shaders. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen7: Use the base_level field of the sampler to handle GL's BASE_LEVEL.Eric Anholt2013-08-301-11/+3
| | | | | | | This avoids the need to get the inter- and intra-tile offset and adjust our miptree info based on them. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2)Ville Syrjälä2013-08-211-3/+2
| | | | | | | | | | | | | | | | IVB/BYT also has the same L3 cacheability control in MOCS as HSW, so let's make use of it. pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most other things show less gains/no regressions, except furmark which loses some 10 points. I didn't have a BYT at hand for testing. v2: Don't check (brw->gen == 7) in gen7 functions. (chadv) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
* i965: Use SURF_INDEX_DRAW() for drawbuffer binding table indices.Kenneth Graunke2013-08-191-6/+8
| | | | | | | | | | | | | | | | | | | | | SURF_INDEX_DRAW() has been the identity function since the dawn of time, and both the shader code and binding table upload code relied on that, simply using X rather than SURF_INDEX_DRAW(X). Even if that continues to be true, using the macro clarifies the code. The comment about draw buffers needing to be first in order for headerless render target writes to work turned out to be wrong; with this change, SURF_INDEX_DRAW can be changed to arbitrary indices and everything continues working. The confusion was over the "Render Target Index" field in the FB write message header. If it were a binding table index, then RT 0 would have to be at index 0 for headerless FB writes to work. However, it's actually an index into the blend state table, so there's no problem. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: Paul Berry <stereotype441@gmail.com>
* i965/hsw: Change L3 MOCS of SURFACE_STATChad Versace2013-07-181-1/+5
| | | | | | | | Change from "not cacheable" to "cacheable" in L3. Do so for the draw upload path and blorp. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
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