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path: root/lib/Target/CellSPU/SPUNodes.td
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* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix memory access lowering on SPU, addingKalle Raiskila2010-11-121-4/+6
| | | | | | | | | | | | | support for the case where alignment<value size. These cases were silently miscompiled before this patch. Now they are overly verbose -especially storing is- and any front-end should still avoid misaligned memory accesses as much as possible. The bit juggling algorithm added here probably has some room for improvement still. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some dead code from SPU BE that remainedKalle Raiskila2010-08-241-6/+0
| | | | | | | from 64bit vector support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111910 91177308-0d34-0410-b5e6-96231b3b80d8
* Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila2010-08-091-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
* Flag SPU's function call sequence together. Kalle Raiskila2010-06-081-1/+1
| | | | | | | | Discussed here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032107.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105601 91177308-0d34-0410-b5e6-96231b3b80d8
* set SDNPVariadic on nodes throughout the rest of the targets thatChris Lattner2010-03-191-1/+2
| | | | | | | need them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
* disambiguate some types, add a fixme about some Chris Lattner2010-03-081-1/+1
| | | | | | | inconsistent intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97959 91177308-0d34-0410-b5e6-96231b3b80d8
* 128-bit sign extension and vector shift cleanups, contributed by Ken WernerScott Michel2009-08-241-3/+3
| | | | | | | (IBM). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79949 91177308-0d34-0410-b5e6-96231b3b80d8
* - Convert remaining i64 custom lowering into custom instruction emissionScott Michel2009-01-151-8/+16
| | | | | | | | | | | | | | sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom DAG node types as needed. - i64 mul is now a legal instruction, but emits an instruction sequence that stretches tblgen and the imagination, as well as violating laws of several small countries and most southern US states (just kidding, but looking at a function with 80+ parameters is really weird and just plain wrong.) - Update tests as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62254 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-061-10/+0
| | | | | | | | - Add preliminary support for v2i32; load/store generates the right code but there's a lot work to be done to make this vector type operational. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61829 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-051-10/+0
| | | | | | | | | | | - Fix (brcond (setq ...)) bug, where BRNZ should have been used vice BRZ. - Kill unused/unnecessary nodes in SPUNodes.td - Beef out the i64operations.c test harness to use a lot of unaligned loads, test loops and LLVM loop/basic block optimizations; run the test harness successfully on real Cell hardware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61664 91177308-0d34-0410-b5e6-96231b3b80d8
* - Start moving target-dependent nodes that could be represented by anScott Michel2008-12-301-29/+0
| | | | | | | | | | | | | | instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
* - Various '#if 0' cleanups.Scott Michel2008-12-291-18/+12
| | | | | | | | | | - Move v4i32, i32 mul into SPUInstrInfo.td, with a few more instruction cleanups there as well. - Make SMUL_LOHI, UMUL_LOHI competely illegal for Cell SPU, to better assist Chris to see the problem in bug 3101. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61464 91177308-0d34-0410-b5e6-96231b3b80d8
* - Remove Tilmann's custom truncate lowering: it completely hosed overScott Michel2008-12-271-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | DAGcombine's ability to find reasons to remove truncates when they were not needed. Consequently, the CellSPU backend would produce correct, but _really slow and horrible_, code. Replaced with instruction sequences that do the equivalent truncation in SPUInstrInfo.td. - Re-examine how unaligned loads and stores work. Generated unaligned load code has been tested on the CellSPU hardware; see the i32operations.c and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be toy test code, it does prove that some real world code does compile correctly.) - Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc fault because i64 ult is not yet implemented.) - Added i64 eq and neq for setcc and select/setcc; started new instruction information file for them in SPU64InstrInfo.td. Additional i64 operations should be added to this file and not to SPUInstrInfo.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61447 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2008-12-041-12/+0
| | | | | | | | | | | | | | | | | | | | | | | - First patch from Nehal Desai, a new contributor at Aerospace. Nehal's patch fixes sign/zero/any-extending loads for integers and floating point. Example code, compiled w/o debugging or optimization where he first noticed the bug: int main(void) { float a = 99.0; printf("%d\n", a); return 0; } Verified that this code actually works on a Cell SPU. Changes by Scott Michel: - Fix bug in the value type list constructed by SPUISD::LDRESULT to include both the load result's result and chain, not just the chain alone. - Simplify LowerLOAD and remove extraneous and unnecessary chains. - Remove unused SPUISD pseudo instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60526 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2008-11-241-5/+2
| | | | | | | | | | | (a) Improve the extract element code: there's no need to do gymnastics with rotates into the preferred slot if a shuffle will do the same thing. (b) Rename a couple of SPUISD pseudo-instructions for readability and better semantic correspondence. (c) Fix i64 sign/any/zero extension lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59965 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU: Fix bug 3056. Varadic extract_element was not implemented (nor was itScott Michel2008-11-221-1/+1
| | | | | | | ever conceived to occur). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59891 91177308-0d34-0410-b5e6-96231b3b80d8
* Add necessary 64-bit support so that gcc frontend compiles (mostly). CurrentScott Michel2008-06-021-15/+26
| | | | | | | | issue is operand promotion for setcc/select... but looks like the fundamental stuff is implemented for CellSPU. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51884 91177308-0d34-0410-b5e6-96231b3b80d8
* Bug fixes and updates for CellSPU, syncing up with trunk. Most notableScott Michel2008-04-301-1/+2
| | | | | | | | | fixes are target-specific lowering of frame indices, fix constants generated for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor- TargetNode(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50462 91177308-0d34-0410-b5e6-96231b3b80d8
* - Fix support for "special" i64 immediates that can be loadedScott Michel2008-03-051-1/+1
| | | | | | | | | | | | using IL, ILA, et. al. v2i64 and i64 are now supported by the select bits (SELB) instruction. - Add missing comparison operations (testcase forthcoming) - More multiclass refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47973 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge current work back to tree to minimize diffs and drift. Major highlightsScott Michel2008-02-231-44/+25
| | | | | | | | | | | | | | | for CellSPU modifications: - SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend. - Other improvements based on refactoring effort in SPUISelLowering.cpp, esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and rotates are now eliminiated, other scalar-to-vector-to-scalar silliness is also eliminated. - 64-bit operations are being implemented, _muldi3.c gcc runtime now compiles and generates the right code. More work still needs to be done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47532 91177308-0d34-0410-b5e6-96231b3b80d8
* More cleanups for CellSPU:Scott Michel2008-01-301-4/+0
| | | | | | | | | | - Expand tabs... (poss 80-col violations, will get them later...) - Consolidate logic for SelectDFormAddr and SelectDForm2Addr into a single function, simplifying maintenance. Also reduced custom instruction generation for SPUvecinsert/INSERT_MASK. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46544 91177308-0d34-0410-b5e6-96231b3b80d8
* Overhaul Cell SPU's addressing mode internals so that there are nowScott Michel2008-01-291-16/+5
| | | | | | | | | | | | | | | only two addressing mode nodes, SPUaform and SPUindirect (vice the three previous ones, SPUaform, SPUdform and SPUxform). This improves code somewhat because we now avoid using reg+reg addressing when it can be avoided. It also simplifies the address selection logic, which was the main point for doing this. Also, for various global variables that would be loaded using SPU's A-form addressing, prefer D-form offs[reg] addressing, keeping the base in a register if the variable is used more than once. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46483 91177308-0d34-0410-b5e6-96231b3b80d8
* Forward progress: crtbegin.c now compiles successfully!Scott Michel2008-01-171-0/+4
| | | | | | | | | | | | | | Fixed CellSPU's A-form (local store) address mode, so that all globals, externals, constant pool and jump table symbols are now wrapped within a SPUISD::AFormAddr pseudo-instruction. This now identifies all local store memory addresses, although it requires a bit of legerdemain during instruction selection to properly select loads to and stores from local store, properly generating "LQA" instructions. Also added mul_ops.ll test harness for exercising integer multiplication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46142 91177308-0d34-0410-b5e6-96231b3b80d8
* rename SDTRet -> SDTNone.Chris Lattner2008-01-151-1/+1
| | | | | | | Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
* More CellSPU refinement and progress:Scott Michel2008-01-111-0/+6
| | | | | | | | | | | | | | | | | | | | | - Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45851 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Updated source file headers to llvm coding standard.Scott Michel2007-12-051-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44597 91177308-0d34-0410-b5e6-96231b3b80d8
* Main CellSPU backend files checked in. Intrinsics and autoconf filesScott Michel2007-12-051-0/+219
remain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44595 91177308-0d34-0410-b5e6-96231b3b80d8
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