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* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-283-3/+3
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-1/+3
* Allow subtarget selection of the default MachineScheduler and document the in...Andrew Trick2013-09-201-4/+12
* Replace some unnecessary vector copies with references.Benjamin Kramer2013-09-151-1/+1
* Rename variables for consistency.Eli Friedman2013-09-111-3/+3
* Fix unused variables.Eli Friedman2013-09-102-4/+0
* mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness...Andrew Trick2013-08-302-6/+6
* Remove use of forbidden 'iostream' header.Bill Wendling2013-08-211-13/+11
* Remove unused stdio.h includesDmitri Gribenko2013-08-181-1/+0
* Refactor isInTailCallPosition handlingTim Northover2013-08-062-0/+15
* Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for ...NAKAMURA Takumi2013-08-061-2/+2
* Fix a memory leak in the hexagon scheduler. We call initialize here moreChandler Carruth2013-07-271-0/+2
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s...Craig Topper2013-07-144-11/+11
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-041-5/+0
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-0/+5
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-031-5/+0
* Hexagon: Avoid unused variable warnings in Release builds.Benjamin Kramer2013-07-021-6/+2
* Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...Richard Trieu2013-07-011-7/+5
* Change assert(0 && "text") to llvm_unreachable(0 && "text")Richard Trieu2013-06-281-2/+2
* Fix broken asserts that never fire.Richard Trieu2013-06-281-2/+2
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-222-3/+3
* Access the TargetLoweringInfo from the TargetMachine object instead of cachin...Bill Wendling2013-06-193-12/+12
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineI...David Blaikie2013-06-162-15/+0
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-2/+2
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-079-19/+25
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-2/+2
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-2/+2
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-291-2/+3
* Hexagon: Typo fix.Jyotsna Verma2013-05-281-5/+5
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-255-45/+45
* Hexagon: Make helper functions static.Benjamin Kramer2013-05-232-3/+5
* Hexagon: SelectionDAG should not use MVT::Other to check the legality of BR_CC.Jyotsna Verma2013-05-211-1/+0
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-181-1/+1
* Don't cast away constness.Benjamin Kramer2013-05-171-2/+2
* Remove dead calls to addFrameMove.Rafael Espindola2013-05-161-25/+0
* Hexagon: Pass to replace tranfer/copy instructions into combine instructionJyotsna Verma2013-05-145-0/+686
* Hexagon: Add patterns to generate 'combine' instructions.Jyotsna Verma2013-05-141-0/+87
* Hexagon: ArePredicatesComplement should not restrict itself to TFRs.Jyotsna Verma2013-05-141-5/+31
* Hexagon: Remove dead-code after unconditional return from addPreSched2.Jyotsna Verma2013-05-141-3/+0
* Suppress GCC compiler warnings in release builds about variables that are onlyDuncan Sands2013-05-131-0/+1
* Remove the MachineMove class.Rafael Espindola2013-05-132-4/+6
* Change getFrameMoves to return a const reference.Rafael Espindola2013-05-111-5/+3
* Fix unused variable error.Jyotsna Verma2013-05-101-2/+1
* Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.Jyotsna Verma2013-05-104-707/+81
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-108-703/+170
* Remove unused argument.Rafael Espindola2013-05-103-6/+4
* Remove unused function.Rafael Espindola2013-05-102-11/+0
* Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.Jyotsna Verma2013-05-093-593/+46
* Hexagon: Use relation map for getMatchingCondBranchOpcode() and Jyotsna Verma2013-05-091-535/+5
* Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma2013-05-077-2/+199
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