| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update aosp/master LLVM for rebase to r230699. | Stephen Hines | 2015-03-23 | 1 | -1571/+1110 |
| * | Update aosp/master LLVM for rebase to r222494. | Stephen Hines | 2014-12-02 | 1 | -176/+451 |
| * | Update LLVM for rebase to r212749. | Stephen Hines | 2014-07-21 | 1 | -36/+216 |
| * | Update LLVM for 3.5 rebase (r209712). | Stephen Hines | 2014-05-29 | 1 | -37/+110 |
| * | Update to LLVM 3.5a. | Stephen Hines | 2014-04-24 | 1 | -556/+958 |
| * | Merging r195129: | Bill Wendling | 2013-11-20 | 1 | -2/+2 |
| * | Lift alignment restrictions on load folding for a significant portion of AVX ... | Craig Topper | 2013-11-05 | 1 | -166/+166 |
| * | Fix PR17764 | Michael Liao | 2013-11-02 | 1 | -1/+1 |
| * | X86: Custom lower sext v16i8 to v16i16, and the corresponding truncate. | Benjamin Kramer | 2013-10-23 | 1 | -0/+3 |
| * | X86: Custom lower zext v16i8 to v16i16. | Benjamin Kramer | 2013-10-23 | 1 | -0/+2 |
| * | Replace (V)MOVZDI2PDIrr/rm instructions with patterns that select (V)MOVDI2PD... | Craig Topper | 2013-10-22 | 1 | -35/+22 |
| * | X86 vector element shift-by-immediate instructions take i8 immediates. Make | Lang Hames | 2013-10-21 | 1 | -6/+6 |
| * | Remove x86_sse42_crc32_64_8 intrinsic. It has no functional difference from x... | Craig Topper | 2013-10-15 | 1 | -6/+9 |
| * | Create classes to reduce the size of the tablegen entries for the CRC32 instr... | Craig Topper | 2013-10-14 | 1 | -66/+33 |
| * | Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instru... | Craig Topper | 2013-10-14 | 1 | -74/+47 |
| * | Add disassembler support for SSE4.1 register/register form of PEXTRW. There i... | Craig Topper | 2013-10-14 | 1 | -0/+7 |
| * | Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the ... | Craig Topper | 2013-10-14 | 1 | -2/+10 |
| * | Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only produ... | Craig Topper | 2013-10-14 | 1 | -4/+8 |
| * | Mark some more instructions as CodeGenOnly. Remove filters from the disassemb... | Craig Topper | 2013-10-12 | 1 | -17/+19 |
| * | Allow non-AVX form of pmovmskb to take a GR64 operand. | Craig Topper | 2013-10-10 | 1 | -0/+2 |
| * | Remove duplicate instructions. | Craig Topper | 2013-10-10 | 1 | -16/+0 |
| * | AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. | Elena Demikhovsky | 2013-10-09 | 1 | -1/+4 |
| * | Mark some instructions as CodeGenOnly since they aren't needed by the assembl... | Craig Topper | 2013-10-09 | 1 | -65/+73 |
| * | Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. Thi... | Craig Topper | 2013-10-09 | 1 | -4/+4 |
| * | Remove some instructions that existed to provide aliases to the assembler. Ca... | Craig Topper | 2013-10-08 | 1 | -27/+10 |
| * | Remove some instructions that seem to only exist to trick the filtering check... | Craig Topper | 2013-10-07 | 1 | -12/+0 |
| * | Remove FsMOVAPSrr and friends. They have no patterns and are no longer select... | Craig Topper | 2013-10-07 | 1 | -21/+4 |
| * | Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to registe... | Craig Topper | 2013-10-07 | 1 | -1/+1 |
| * | Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS i... | Craig Topper | 2013-09-27 | 1 | -1/+1 |
| * | Removal some duplicate patterns. | Craig Topper | 2013-09-27 | 1 | -8/+0 |
| * | Fixing Intel format of the vshufpd instruction. | Yunzhong Gao | 2013-09-27 | 1 | -2/+2 |
| * | Lift alignment restrictions on load/store folding of VEXTRACTI128/VINSERTI128. | Craig Topper | 2013-09-20 | 1 | -12/+12 |
| * | Lift alignment restrictions for load/store folding on VINSERTF128/VEXTRACTF12... | Craig Topper | 2013-09-18 | 1 | -10/+10 |
| * | Add llvm.x86.* intrinsics for Intel SHA Extensions | Ben Langmuir | 2013-09-17 | 1 | -14/+26 |
| * | Make F16C feature flag imply AVX rather than just checking both at the patterns. | Craig Topper | 2013-09-16 | 1 | -1/+1 |
| * | Add the remaining Intel SHA instructions | Ben Langmuir | 2013-09-14 | 1 | -0/+27 |
| * | Adds support for Atom Silvermont (SLM) - -march=slm | Preston Gurd | 2013-09-13 | 1 | -111/+184 |
| * | Partial support for Intel SHA Extensions (sha1rnds4) | Ben Langmuir | 2013-09-12 | 1 | -0/+16 |
| * | AVX-512: implemented extractelement with variable index. | Elena Demikhovsky | 2013-09-12 | 1 | -0/+12 |
| * | Add neverHasSideEffects=1 on a couple move instructions. | Craig Topper | 2013-09-08 | 1 | -1/+1 |
| * | AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS | Elena Demikhovsky | 2013-08-28 | 1 | -23/+23 |
| * | AVX-512: added conversion instructions. | Elena Demikhovsky | 2013-08-27 | 1 | -19/+27 |
| * | AVX-512: Added shuffle instructions - | Elena Demikhovsky | 2013-08-26 | 1 | -2/+2 |
| * | AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ | Elena Demikhovsky | 2013-08-20 | 1 | -1/+1 |
| * | Move AVX and non-AVX replication inside a couple multiclasses to avoid repeat... | Craig Topper | 2013-08-20 | 1 | -87/+60 |
| * | AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions. | Elena Demikhovsky | 2013-08-18 | 1 | -11/+11 |
| * | X86: Turn fp selects into mask operations. | Benjamin Kramer | 2013-08-04 | 1 | -2/+2 |
| * | AVX-512 set: added VEXTRACTPS instruction | Elena Demikhovsky | 2013-08-04 | 1 | -1/+1 |
| * | Added INSERT and EXTRACT intructions from AVX-512 ISA. | Elena Demikhovsky | 2013-07-31 | 1 | -80/+80 |
| * | Changed register names (and pointer keywords) to be lower case when using Int... | Craig Topper | 2013-07-31 | 1 | -10/+10 |
