aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/X86/X86InstrSSE.td
Commit message (Collapse)AuthorAgeFilesLines
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-1571/+1110
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-176/+451
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-36/+216
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-37/+110
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-556/+958
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Merging r195129:Bill Wendling2013-11-201-2/+2
| | | | | | | | | | | | ------------------------------------------------------------------------ r195129 | mcinally | 2013-11-19 06:36:00 -0800 (Tue, 19 Nov 2013) | 2 lines Fix assembly operands for the SSE2 cvtsd2ss instruction. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195218 91177308-0d34-0410-b5e6-96231b3b80d8
* Lift alignment restrictions on load folding for a significant portion of AVX ↵Craig Topper2013-11-051-166/+166
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194048 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR17764Michael Liao2013-11-021-1/+1
| | | | | | | | | - When selecting BLEND from vselect, the operands need swapping as due to the difference between vselect and SSE/AVX's BLEND insn git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193900 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Custom lower sext v16i8 to v16i16, and the corresponding truncate.Benjamin Kramer2013-10-231-0/+3
| | | | | | Also update the cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193270 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Custom lower zext v16i8 to v16i16.Benjamin Kramer2013-10-231-0/+2
| | | | | | | | | | | | | | | | | On sandy bridge (PR17654) we now get vpxor %xmm1, %xmm1, %xmm1 vpunpckhbw %xmm1, %xmm0, %xmm2 vpunpcklbw %xmm1, %xmm0, %xmm0 vinsertf128 $1, %xmm2, %ymm0, %ymm0 On haswell it's a simple vpmovzxbw %xmm0, %ymm0 There is a maze of duplicated and dead transforms and patterns in this area. Remove the dead custom lowering of zext v8i16 to v8i32, that's already handled by LowerAVXExtend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193262 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace (V)MOVZDI2PDIrr/rm instructions with patterns that select ↵Craig Topper2013-10-221-35/+22
| | | | | | (V)MOVDI2PDIrr/rm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193146 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 vector element shift-by-immediate instructions take i8 immediates. MakeLang Hames2013-10-211-6/+6
| | | | | | | | | | | | | | | | the instruction defenitions and ISEL reflect this. Prior to this patch these instructions took an i32i8imm, and the high bits were dropped during encoding. This led to incorrect behavior for shifts by immediates higher than 255. This patch fixes that issue by detecting large immediate shifts and returning constant zero (for logical shifts) or capping the shift amount at an encodable value (for arithmetic shifts). Fixes <rdar://problem/14968098> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193096 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove x86_sse42_crc32_64_8 intrinsic. It has no functional difference from ↵Craig Topper2013-10-151-6/+9
| | | | | | x86_sse42_crc32_32_8 and was not mapped to a clang builtin. I'm not even sure why this form of the instruction is even called out explicitly in the docs. Also add AutoUpgrade support to convert it into the other intrinsic with appropriate trunc and zext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192672 91177308-0d34-0410-b5e6-96231b3b80d8
* Create classes to reduce the size of the tablegen entries for the CRC32 ↵Craig Topper2013-10-141-66/+33
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192568 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-141-74/+47
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembler support for SSE4.1 register/register form of PEXTRW. There ↵Craig Topper2013-10-141-0/+7
| | | | | | is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the ↵Craig Topper2013-10-141-2/+10
| | | | | | disassembler tables. Add PINSRWrr64i to complement the AVX version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only ↵Craig Topper2013-10-141-4/+8
| | | | | | produce a 1-bit result so we can just use SUBREG_TO_REG to extend the 32-bit versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192562 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark some more instructions as CodeGenOnly. Remove filters from the ↵Craig Topper2013-10-121-17/+19
| | | | | | disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192522 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow non-AVX form of pmovmskb to take a GR64 operand.Craig Topper2013-10-101-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192341 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove duplicate instructions.Craig Topper2013-10-101-16/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192340 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-091-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark some instructions as CodeGenOnly since they aren't needed by the ↵Craig Topper2013-10-091-65/+73
| | | | | | assembler or disassembler. Disassembler already filtered them, but asm parser still had them in its tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192271 91177308-0d34-0410-b5e6-96231b3b80d8
* Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. ↵Craig Topper2013-10-091-4/+4
| | | | | | This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192266 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some instructions that existed to provide aliases to the assembler. ↵Craig Topper2013-10-081-27/+10
| | | | | | Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some instructions that seem to only exist to trick the filtering ↵Craig Topper2013-10-071-12/+0
| | | | | | checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove FsMOVAPSrr and friends. They have no patterns and are no longer ↵Craig Topper2013-10-071-21/+4
| | | | | | selected anywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192089 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to ↵Craig Topper2013-10-071-1/+1
| | | | | | | | | | register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192088 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS ↵Craig Topper2013-09-271-1/+1
| | | | | | is used in AVX512 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191489 91177308-0d34-0410-b5e6-96231b3b80d8
* Removal some duplicate patterns.Craig Topper2013-09-271-8/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191488 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixing Intel format of the vshufpd instruction.Yunzhong Gao2013-09-271-2/+2
| | | | | | | | Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191481 91177308-0d34-0410-b5e6-96231b3b80d8
* Lift alignment restrictions on load/store folding of VEXTRACTI128/VINSERTI128.Craig Topper2013-09-201-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191073 91177308-0d34-0410-b5e6-96231b3b80d8
* Lift alignment restrictions for load/store folding on ↵Craig Topper2013-09-181-10/+10
| | | | | | VINSERTF128/VEXTRACTF128. Fixes PR17268. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190916 91177308-0d34-0410-b5e6-96231b3b80d8
* Add llvm.x86.* intrinsics for Intel SHA ExtensionsBen Langmuir2013-09-171-14/+26
| | | | | | | | | Add llvm.x86.* intrinsics for all of the Intel SHA Extensions instructions, as well as tests. Also remove mayLoad and hasSideEffects, which can be inferred from the instruction patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190864 91177308-0d34-0410-b5e6-96231b3b80d8
* Make F16C feature flag imply AVX rather than just checking both at the patterns.Craig Topper2013-09-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190775 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the remaining Intel SHA instructionsBen Langmuir2013-09-141-0/+27
| | | | | | | | Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190754 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-111/+184
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-121-0/+16
| | | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: implemented extractelement with variable index.Elena Demikhovsky2013-09-121-0/+12
| | | | | | | Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
* Add neverHasSideEffects=1 on a couple move instructions.Craig Topper2013-09-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190259 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABSElena Demikhovsky2013-08-281-23/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189472 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added conversion instructions.Elena Demikhovsky2013-08-271-19/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189349 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added shuffle instructions - Elena Demikhovsky2013-08-261-2/+2
| | | | | | | | VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN single and double forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189215 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQElena Demikhovsky2013-08-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188786 91177308-0d34-0410-b5e6-96231b3b80d8
* Move AVX and non-AVX replication inside a couple multiclasses to avoid ↵Craig Topper2013-08-201-87/+60
| | | | | | repeating each instruction for both individually. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188743 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions.Elena Demikhovsky2013-08-181-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188637 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Turn fp selects into mask operations.Benjamin Kramer2013-08-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | double test(double a, double b, double c, double d) { return a<b ? c : d; } before: _test: ucomisd %xmm0, %xmm1 ja LBB0_2 movaps %xmm3, %xmm2 LBB0_2: movaps %xmm2, %xmm0 after: _test: cmpltsd %xmm1, %xmm0 andpd %xmm0, %xmm2 andnpd %xmm3, %xmm0 orpd %xmm2, %xmm0 Small speedup on Benchmarks/SmallPT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187706 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512 set: added VEXTRACTPS instructionElena Demikhovsky2013-08-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187705 91177308-0d34-0410-b5e6-96231b3b80d8
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-311-80/+80
| | | | | | | | | | All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-311-10/+10
| | | | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-01-07 04:47:28 +0000