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* Fix dubious type name similar to member name.Sean Silva2013-06-115-5/+5
* [yaml2obj] Initial ELF support.Sean Silva2013-06-107-0/+79
* ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.Tim Northover2013-06-105-3/+36
* X86: Stop LEA64_32r doing unspeakable things to its arguments.Tim Northover2013-06-103-6/+8
* [PowerPC] Support extended sc mnemonicUlrich Weigand2013-06-101-0/+2
* [PowerPC] Support branch mnemonics with implied CR0Ulrich Weigand2013-06-101-1/+197
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-106-0/+22
* [NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore...Justin Holewinski2013-06-101-0/+10
* Add test for ARM FastISel load/store register classesJF Bastien2013-06-101-0/+70
* Fix a regression I introduced when I expanded the complex pseudos inReed Kotler2013-06-091-0/+6406
* Refine the ARM EHABI test cases.Logan Chien2013-06-099-413/+323
* Fix ARM unwind opcode assembler in several cases.Logan Chien2013-06-097-8/+314
* Removed PackedDouble domain from scalar instructions. Added more formats for ...Elena Demikhovsky2013-06-092-3/+3
* Make DeadArgumentElimination more conservative on variadic functionsTim Northover2013-06-091-0/+38
* [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc bac...Venkatraman Govindaraju2013-06-081-0/+47
* ARM: fix VMOVvnf32 decoding when ambiguous with VCVTAmaury de la Vieuville2013-06-081-0/+7
* ARM: enforce SRS decoding constraintsAmaury de la Vieuville2013-06-081-3/+7
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-082-0/+13
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-081-0/+8
* Fix a potential bug in r183584.Shuxin Yang2013-06-081-22/+0
* Reapply r183552. This time, use a standard type for the option to avoid templateQuentin Colombet2013-06-082-0/+48
* R600: Anti dep better handled in tex clauseVincent Lejeune2013-06-071-0/+24
* Add missing zextloadi1 to i64 patterns. PR16721.Jakob Stoklund Olesen2013-06-071-0/+8
* Fix an assertion in MemCpyOpt pass.Shuxin Yang2013-06-071-0/+39
* Disallow i64 div/rem in PPC32 counter loopsHal Finkel2013-06-071-0/+93
* Revert commits related to stack warning.Quentin Colombet2013-06-072-48/+0
* Explicit triple in warn stack size test cases to not depend on OS.Quentin Colombet2013-06-072-4/+4
* R600: Fix calculation of stack offset in AMDGPUFrameLoweringTom Stellard2013-06-071-0/+33
* R600: Fix the fetch limits for R600 generation GPUsTom Stellard2013-06-072-0/+129
* Add a backend option to warn on a given stack size limit.Quentin Colombet2013-06-072-0/+48
* ARM FastISel integer sext/zext improvementsJF Bastien2013-06-079-29/+188
* Teach AsmPrinter how to print odd constants.Quentin Colombet2013-06-073-0/+52
* Fix a typo in asm string of BP* family of instructions. With this fixRoman Divacky2013-06-071-2/+2
* Support OpenBSD's native frame protection conventions.Rafael Espindola2013-06-071-0/+5
* [objc-arc] Ensure that the cfg path count does not overflow when we multiply ...Michael Gottesman2013-06-071-3/+531
* [Sparc]: Use cmp instruction instead of subcc to compare integers.Venkatraman Govindaraju2013-06-074-17/+17
* Move the test for the data in code into the ARM directory as it is an ARMKevin Enderby2013-06-061-0/+0
* Add a testcase from pr16244.Rafael Espindola2013-06-061-0/+10
* Teach llvm-objdump with the -macho parser how to use the data in code tableKevin Enderby2013-06-062-0/+7
* Print symbol names in relocations when dumping COFF as YAML.Rafael Espindola2013-06-063-12/+12
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-051-0/+30
* Don't hide the first ELF symbol.Rafael Espindola2013-06-054-1/+37
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-0510-10/+10
* [mips] brcond + setgt/setugt instruction selection patterns.Akira Hatanaka2013-06-051-0/+134
* [PATCH] Fix VGATHER* operand constraintsMichael Liao2013-06-051-0/+18
* This is a simple patch that changes RRX and RRXS to accept all registers as o...Mihai Popa2013-06-052-0/+47
* PR15662: Optimized debug info produces out of order function parametersDavid Blaikie2013-06-051-0/+73
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-051-0/+32
* Don't print default values for NumberOfAuxSymbols and AuxiliaryData.Rafael Espindola2013-06-051-0/+1
* Revert "R600: Add a pass that merge Vector Register"Rafael Espindola2013-06-051-30/+0
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