summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_defines.h
Commit message (Expand)AuthorAgeFilesLines
* i965/skl: Set the pulls bary bit in 3DSTATE_PS_EXTRANeil Roberts2015-07-061-0/+1
* i965/gen9: Don't use encrypted MOCSBen Widawsky2015-06-231-2/+2
* i965/gen9: Disable Mip Tail for YF/YS tiled surfacesAnuj Phogat2015-06-161-0/+3
* i965/gen9: Set tiled resource mode in surface stateAnuj Phogat2015-06-161-0/+6
* i965/fs: Implement support for ir_barrierJordan Justen2015-06-121-0/+5
* i965: Add GATEWAY_SFID definitionsJordan Justen2015-06-121-0/+8
* i965: Create a shader_dispatch_mode enum to replace VS/GS fields.Kenneth Graunke2015-06-011-3/+2
* i965: Add Gen9 surface state decodingBen Widawsky2015-05-181-0/+2
* i965: Add gen8 surface state debug infoBen Widawsky2015-05-181-1/+3
* i965: Add gen7+ sampler state to batch debugBen Widawsky2015-05-181-0/+1
* i965: Use predicate enable bit for conditional rendering w/o stallingNeil Roberts2015-05-121-0/+1
* i965/gen6: setup limits for ARB_viewport_arrayChris Forbes2015-05-061-1/+1
* i965: Introduce the FIND_LIVE_CHANNEL pseudo-opcode.Francisco Jerez2015-05-041-0/+8
* i965: Introduce the BROADCAST pseudo-opcode.Francisco Jerez2015-05-041-0/+6
* i965: Add memory fence opcode.Francisco Jerez2015-05-041-0/+2
* i965: Add typed surface access opcodes.Francisco Jerez2015-05-041-0/+4
* i965: Add untyped surface write opcode.Francisco Jerez2015-05-041-0/+1
* i965/cs: Emit MEDIA_STATE_FLUSH after WALKERJordan Justen2015-05-021-0/+1
* i965/cs: Implement brw_emit_gpgpu_walkerJordan Justen2015-05-021-0/+13
* i965/cs: Upload brw_cs_stateJordan Justen2015-05-021-0/+20
* i965/cs: Add CS_OPCODE_CS_TERMINATEJordan Justen2015-05-021-0/+5
* i965/ps: Use SET_FIELD() for sampler countTopi Pohjolainen2015-04-301-0/+1
* i965/fs: Combine pixel center calculation into one inst.Matt Turner2015-04-211-0/+2
* i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.Matt Turner2015-04-211-2/+0
* i965/skl: Add the header for constant loads outside of the generatorNeil Roberts2015-04-161-0/+1
* i965: Add missing defines for render cache messages.Francisco Jerez2015-03-021-1/+7
* i965/vec4: Add and use byte-MOV instruction for unpack 4x8.Matt Turner2015-02-191-0/+1
* i965: Fix integer border color on Haswell.Kenneth Graunke2015-02-091-0/+1
* i965/skl: Always use a header for SIMD4x2 sampler messagesKristian Høgsberg2015-01-081-0/+5
* i965: Add new SIMD8 VS prog data flagKristian Høgsberg2014-12-101-0/+2
* i965: Add SIMD8 URB write low-level IR instructionKristian Høgsberg2014-12-101-0/+3
* i965/vec4: Allow CSE on uniform-vec4 expansion MOVs.Matt Turner2014-12-051-0/+1
* i965: Move PSCDEPTH calculations from draw time to compile time.Kenneth Graunke2014-12-041-8/+9
* i965/fs: Pass key->render_to_fbo via src1 of FS_OPCODE_DDY_*.Kenneth Graunke2014-11-271-0/+4
* i965/fs: Handle derivative quality decisions in the front-end.Kenneth Graunke2014-11-271-8/+4
* i965/vec4: Add VEC4_OPCODE_PACK_4_BYTES.Matt Turner2014-11-251-0/+2
* i965/disasm: Properly decode branch_ctrl (gen8+)Ben Widawsky2014-11-201-0/+1
* i965: Set Line Width correctly on Cherryview and Skylake.Kenneth Graunke2014-11-081-0/+1
* i965: Convert stride/width/execution size macros into enums.Matt Turner2014-11-061-28/+33
* i965/skl: Use new MOCS for SKLKristian Høgsberg2014-11-031-0/+7
* i965/skl: Update Viewport Z Clip Test Enable bits for Skylake.Kenneth Graunke2014-11-031-0/+2
* i965/skl: Update stencil reference handling for Skylake.Kenneth Graunke2014-11-031-0/+5
* i965/skl: Update 3DSTATE_SBE for Skylake.Damien Lespiau2014-11-031-0/+6
* i965: Add a BRW_MOCS_PTE #define.Kenneth Graunke2014-10-091-3/+7
* i965: Fix spelling of GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHMChris Forbes2014-10-011-1/+1
* i965: Delete intel_chipset.h.Kenneth Graunke2014-09-291-2/+0
* i965: Add BRW_OPCODE_NENOP for G45.Matt Turner2014-09-251-0/+1
* i965/gen6/gs: Add an additional parameter to the FF_SYNC opcode.Samuel Iglesias Gonsalvez2014-09-191-0/+4
* i965/gen6/gs: implement GS_OPCODE_FF_SYNC_SET_PRIMITIVES opcodeSamuel Iglesias Gonsalvez2014-09-191-0/+15
* i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcodeSamuel Iglesias Gonsalvez2014-09-191-0/+9
generated by cgit v1.1 at 2024-07-12 06:11:28 +0000