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* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-23276-11762/+21211
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-02290-1655/+18617
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-21194-555/+3570
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-29319-8859/+22226
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-24474-180258/+47484
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Merging r196104:Bill Wendling2013-12-021-0/+14
| | | | | | | | | | | ------------------------------------------------------------------------ r196104 | rafael | 2013-12-02 06:59:34 -0800 (Mon, 02 Dec 2013) | 1 line Output .eh_frames on COFF too now that the integrated as is used on mingw. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196137 91177308-0d34-0410-b5e6-96231b3b80d8
* Merged from r195975 and r195976.Daniel Sanders2013-12-011-0/+16437
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195975 | zjovanovic | 2013-11-30 19:12:28 +0000 (Sat, 30 Nov 2013) | 1 line Fixed issue with microMIPS long branch. ------------------------------------------------------------------------ r195976 | zjovanovic | 2013-11-30 19:13:15 +0000 (Sat, 30 Nov 2013) | 1 line Test case for issue with microMIPS long branch. ------------------------------------------------------------------------ To expand on those commit messages: The immediate in a MIPS branch is multiplied by the instruction size before use as an offset. For many MIPS ISA's this is 4 bytes, but for microMIPS it is 2 bytes. This commit corrects the scale factor used for microMIPS so that attempts to use large offsets result in a valid sequence of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196043 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r195823 into '.':Bill Wendling2013-12-012-9/+15
| | | | | | | | | | | | | | U lib/MC/MCSectionCOFF.cpp U lib/CodeGen/TargetLoweringObjectFileImpl.cpp U test/MC/COFF/weak-symbol.ll U test/MC/COFF/tricky-names.ll G . --- Recording mergeinfo for reverse merge of r195823 into '.': G . git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196036 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195936:Bill Wendling2013-12-011-0/+17
| | | | | | | | | | | ------------------------------------------------------------------------ r195936 | kevinqin | 2013-11-28 17:29:16 -0800 (Thu, 28 Nov 2013) | 1 line [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196028 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195903:Bill Wendling2013-12-011-1/+3
| | | | | | | | | | | | ------------------------------------------------------------------------ r195903 | haoliu | 2013-11-27 17:07:45 -0800 (Wed, 27 Nov 2013) | 2 lines AArch64: Fix a bug about disassembling post-index load single element to 4 vectors ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196025 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195677:Bill Wendling2013-12-012-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195677 | dpeixott | 2013-11-25 11:11:13 -0800 (Mon, 25 Nov 2013) | 41 lines ARM integrated assembler generates incorrect nop opcode This patch fixes a bug in the assembler that was causing bad code to be emitted. When switching modes in an assembly file (e.g. arm to thumb mode) we would always emit the opcode from the original mode. Consider this small example: $ cat align.s .code 16 foo: add r0, r0 .align 3 add r0, r0 $ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o $ llvm-objdump -triple thumbv7 -d t.o Disassembly of section .text: foo: 0: 00 44 add r0, r0 2: 00 f0 20 e3 blx #4195904 6: 00 00 movs r0, r0 8: 00 44 add r0, r0 This shows that we have actually emitted an arm nop (e320f000) instead of a thumb nop. Unfortunately, this encodes to a thumb branch which causes bad things to happen when compiling assembly code with align directives. The fix is to notify the ARMAsmBackend when we switch mode. The MCMachOStreamer was already doing this correctly. This patch makes the same change for the MCElfStreamer. There is still a bug in the way nops are emitted for alignment because the MCAlignment fragment does not store the correct mode. The ARMAsmBackend will emit nops for the last mode it knew about. In the example above, we still generate an arm nop if we add a `.code 32` to the end of the file. PR18019 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196001 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195803:Bill Wendling2013-12-013-0/+33
| | | | | | | | | | | ------------------------------------------------------------------------ r195803 | mcrosier | 2013-11-26 17:45:58 -0800 (Tue, 26 Nov 2013) | 1 line [AArch64] Add support for NEON scalar floating-point absolute difference. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195994 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195788:Bill Wendling2013-12-013-0/+377
| | | | | | | | | | | | ------------------------------------------------------------------------ r195788 | mcrosier | 2013-11-26 14:17:37 -0800 (Tue, 26 Nov 2013) | 2 lines [AArch64] Add support for NEON scalar floating-point to integer convert instructions. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195993 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195798:Bill Wendling2013-11-272-15/+9
| | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195798 | rafael | 2013-11-26 17:18:37 -0800 (Tue, 26 Nov 2013) | 9 lines Use simple section names for COMDAT sections on COFF. With this patch we use simple names for COMDAT sections (like .text or .bss). This matches the MSVC behavior. When merging it is the COMDAT symbol that is used to decide if two sections should be merged, so there is no point in building a fancy name. This survived a bootstrap on mingw32. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195823 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195148:Bill Wendling2013-11-271-0/+188
| | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195148 | rafael | 2013-11-19 11:52:52 -0800 (Tue, 19 Nov 2013) | 15 lines Support multiple COFF sections with the same name but different COMDAT. This is the first step to fix pr17918. It extends the .section directive a bit, inspired by what the ELF one looks like. The problem with using linkonce is that given .section foo .linkonce.... .section foo .linkonce we would already have switched sections when getting to .linkonce. The cleanest solution seems to be to add the comdat information in the .section itself. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195822 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195682:Bill Wendling2013-11-261-16/+16
| | | | | | | | | | | ------------------------------------------------------------------------ r195682 | rafael | 2013-11-25 12:46:18 -0800 (Mon, 25 Nov 2013) | 1 line Use -triple to fix the test on non-ELF hosts. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195745 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195679:Bill Wendling2013-11-261-2/+25
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195679 | rafael | 2013-11-25 12:15:14 -0800 (Mon, 25 Nov 2013) | 12 lines Don't use nopl in cpus that don't support it. Patch by Mikulas Patocka. I added the test. I checked that for cpu names that gas knows about, it also doesn't generate nopl. The modified cpus: i686 - there are i686-class CPUs that don't have nopl: Via c3, Transmeta Crusoe, Microsoft VirtualBox - see https://bbs.archlinux.org/viewtopic.php?pid=775414 k6, k6-2, k6-3, winchip-c6, winchip2 - these are 586-class CPUs via c3 c3-2 - see https://bugs.archlinux.org/task/19733 as a proof that Via c3 and c3-Nehemiah don't have nopl ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195730 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195591:Bill Wendling2013-11-251-7/+7
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195591 | haoliu | 2013-11-24 17:53:26 -0800 (Sun, 24 Nov 2013) | 5 lines Fixed a bug about disassembling AArch64 post-index load/store single element instructions. ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble will be disassembled into the same instruction st1 {v0b}[0], [x0], x0. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195619 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195330:Bill Wendling2013-11-251-0/+26
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195330 | apazos | 2013-11-21 00:16:15 -0800 (Thu, 21 Nov 2013) | 5 lines Implemented Neon scalar vdup_lane intrinsics. Fixed scalar dup alias and added test case. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195612 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195152:Bill Wendling2013-11-204-19/+13
| | | | | | | | | | | ------------------------------------------------------------------------ r195152 | jacksprat | 2013-11-19 12:53:28 -0800 (Tue, 19 Nov 2013) | 1 line reverts 195057 per request ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195220 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-193-0/+528
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
* implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit ↵Kevin Qin2013-11-192-0/+16
| | | | | | integer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
* Add predicate for AArch64 crypto instructions.Jiangning Liu2013-11-191-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] Support for MicroMips STO refactoring.Jack Carter2013-11-194-13/+19
| | | | | | | | | | | | | | | | | No true functional changes. Change the "hack" name of emitMipsHackSTOCG to emitSymSTO. Remove demonstration code in AsmParser for emitMipsHackSTOCG and emitMipsHackELFFlags. The STO field is in an ELF symbol and is not an explicit directive. That said, we are missing the compliment call in AsmParser and that will need to be addressed soon. XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags. These will built out with following patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "COFF: Emit all MCSymbols rather than filtering out some of them"Reid Kleckner2013-11-183-10/+14
| | | | | | | | This reverts commit r190888, to fix PR17967. The original change wasn't the right way to get @feat.00 into the object file. The right fix is to make @feat.00 be a global symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Update encoding of bnz.v (typo).Matheus Almeida2013-11-181-2/+2
| | | | | | | | Note that there's no hardware yet that relies on that encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Fix immediate value of LSA instruction as it was being wrongly ↵Matheus Almeida2013-11-181-1/+10
| | | | | | | | | | | encoded. The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON]Add mov alias for simd copy instructions.Kevin Qin2013-11-181-10/+36
| | | | | | Set some unspecified bits of INS/DUP to zero as ARMARM requested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
* Use instr mapping for microMIPS in llvm-mc.Zoran Jovanovic2013-11-151-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test case for AArch64 NEON instruction set misc.Kevin Qin2013-11-141-0/+646
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction class SIMD misc.Kevin Qin2013-11-141-0/+1034
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-143-1/+144
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add the general form of BCRRichard Sandiford2013-11-133-0/+144
| | | | | | | At the moment this is just the MC support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in .gpword directive parsing.Vladimir Medic2013-11-131-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194570 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS trap instruction with immediate operands.Zoran Jovanovic2013-11-133-0/+54
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch fixes a bug in floating point operands parsing, when instruction ↵Vladimir Medic2013-11-131-1/+3
| | | | | | alias uses default register operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194562 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: diagnose invalid system LDM/STMTim Northover2013-11-121-0/+5
| | | | | | | | | | | | | The system LDM and STM instructions can't usually writeback to the base register. The one exception is when an LDM is actually an exception-return (i.e. contains PC in the register list). (There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there is no positive test). rdar://problem/15223374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalarChad Rosier2013-11-1210-6/+674
| | | | | | | | copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Add support for MVFR2 which is new in ARMv8Artyom Skrobov2013-11-113-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point ↵Chad Rosier2013-11-113-0/+72
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()Jim Grosbach2013-11-081-0/+73
| | | | | | | | | | On darwin, when trying to create compact unwind info, a .cfi_cfa_def directive would case an llvm_unreachable() to be hit. Back off when we see this directive and generate the regular DWARF style eh_frame. rdar://15406518 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194285 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-083-2992/+218
| | | | | | ARMv8 (Thumb encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-0/+167
| | | | | | ARMv8 (ARM encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194262 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-0/+35
| | | | | | ARMv8 (ARM encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
* Test for microMIPS trap instructions.Zoran Jovanovic2013-11-081-0/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194258 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Update encoding of LDI instruction.Matheus Almeida2013-11-081-4/+4
| | | | | | | | The encoding was updated in MSA r1.07. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 ↵Artyom Skrobov2013-11-084-26/+31
| | | | | | as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS trap instructions 1.Zoran Jovanovic2013-11-072-0/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement gpword directive for mips, test case added. Stype changes using ↵Vladimir Medic2013-11-061-0/+1
| | | | | | clang-format are also included. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 Neon instruction set Perm.Jiangning Liu2013-11-063-0/+626
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
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