aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/Mips/MipsRegisterInfo.td
Commit message (Collapse)AuthorAgeFilesLines
* Clean up code for Mips16 large frame handling.Reed Kotler2013-08-041-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187701 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements parsing of mips FCC register operands. The example ↵Vladimir Medic2013-07-301-0/+9
| | | | | | instructions have been added to test files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Increase the number of floating point condition code registers to eight.Akira Hatanaka2013-07-261-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187234 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Delete register print method MipsInstPrinter::printCPURegs that is notAkira Hatanaka2013-07-261-5/+5
| | | | | | | | | | needed. The generic method printOperand will do. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187231 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use "foreach" loop to make register definitions more concise.Akira Hatanaka2013-07-171-80/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186528 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Increase the number of floating point control registers available to 32.Akira Hatanaka2013-07-011-4/+9
| | | | | | | | | Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch introduces RegisterOperand class into Mips FPU instruction ↵Vladimir Medic2013-06-241-0/+27
| | | | | | definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184716 91177308-0d34-0410-b5e6-96231b3b80d8
* The RenderMethod field in RegisterOperand class sets the name of the method ↵Vladimir Medic2013-06-191-5/+9
| | | | | | on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184292 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-10/+10
| | | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Split the DSP control register and define one register for each field ofAkira Hatanaka2013-05-031-1/+21
| | | | | | | | | | | | | its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix handling of instructions which copy to/from accumulator registers.Akira Hatanaka2013-04-301-2/+4
| | | | | | | | | | | Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Instruction selection patterns for DSP-ASE vector select and compareAkira Hatanaka2013-04-301-0/+4
| | | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka2013-04-181-8/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Change type of accumulator registers to Untyped. Add two more accumulatorAkira Hatanaka2013-03-291-7/+30
| | | | | | | | | register classes for Mips64 and DSP-ASE. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178328 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Set isAllocatable bit of unallocatable register classes to 0.Akira Hatanaka2013-03-141-8/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177128 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-171-1/+1
| | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting 172579Jack Carter2013-01-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
* Akira,Jack Carter2013-01-161-1/+1
| | | | | | | | | | | | | | Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch tackles the problem of parsing Mips Jack Carter2013-01-121-0/+45
| | | | | | | | | | | | | | | | | | | | register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Set HWEncoding field of registers. Use delete functionAkira Hatanaka2012-12-101-29/+20
| | | | | | | getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169760 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use register number instead of name to print register $AT.Akira Hatanaka2012-11-021-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167315 91177308-0d34-0410-b5e6-96231b3b80d8
* 1. Add load/store words from the stackReed Kotler2012-09-281-0/+1
| | | | | | | | | | | 2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and moved other lines for FEXT_RI16 formats to be in the right place in the code. 3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment. 4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164811 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DSP accumulator registers and register class. Remove hi/lo registers.Akira Hatanaka2012-09-261-33/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164719 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MIPS accumulator and DSP control registers.Akira Hatanaka2012-09-211-1/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164429 91177308-0d34-0410-b5e6-96231b3b80d8
* Add stub methods for mips assembly matcher. Akira Hatanaka2012-08-171-0/+3
| | | | | | | Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
* In register classes in MipsRegisterInfo.td, list the registers in ascendingAkira Hatanaka2012-07-111-99/+114
| | | | | | | | | | order of binary encoding. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160073 91177308-0d34-0410-b5e6-96231b3b80d8
* revert r159851.Akira Hatanaka2012-07-061-114/+99
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r158846.Akira Hatanaka2012-07-061-99/+114
| | | | | | | Include file MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r158846.Akira Hatanaka2012-06-201-114/+99
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
* In MipsDisassembler.cpp, instead of defining register class tables, use the onesAkira Hatanaka2012-06-201-99/+114
| | | | | | | | | | | | that are generated by TableGen and are already available in MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen. Also, fix bug in function DecodeAFGR64RegisterClass. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable Mips16 compiler to compile a null program.Akira Hatanaka2012-05-241-0/+2
| | | | | | | | | First code from the Mips16 compiler. Includes trivial test program. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157408 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds the register class for MIPS16 as well as the ability forAkira Hatanaka2012-05-161-0/+7
| | | | | | | | | | | | | | | | llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156958 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-041-12/+4
| | | | | | This information in now computed by TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
* delete useless comment&blankJia Liu2012-02-271-16/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151512 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DWARF numbers of 64-bit registers.Akira Hatanaka2012-02-021-64/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149583 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-181-0/+1
| | | | | | | | | | | | | | | | When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
* Add newline.Akira Hatanaka2011-12-071-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146100 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 64-bit HWR29 register.Akira Hatanaka2011-12-071-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146099 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of 64-bit register files. Add code for returning Mips64's ↵Akira Hatanaka2011-09-231-0/+25
| | | | | | | | | sets of callee-saved registers and reserved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140395 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of 64-bit int registers.Akira Hatanaka2011-09-231-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140366 91177308-0d34-0410-b5e6-96231b3b80d8
* Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment.Akira Hatanaka2011-09-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140324 91177308-0d34-0410-b5e6-96231b3b80d8
* Define a new sub-register index sub_32 for accessing the 32-bit sub-register ofAkira Hatanaka2011-09-221-4/+5
| | | | | | | | | | | a 64-bit integer register. Move the subreg index definitions to the beginning of the file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140319 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definition of 64-bit floating registers used for Mips64.Akira Hatanaka2011-09-221-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140297 91177308-0d34-0410-b5e6-96231b3b80d8
* Make F31 and D15 non-reserved registers.Akira Hatanaka2011-09-091-3/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
* Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen2011-06-151-18/+10
| | | | | | | | | | | | This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen2011-06-091-71/+3
| | | | | | | | | | | | | | | | | | | | The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements the thread local storage. Implemented are GeneralBruno Cardoso Lopes2011-05-311-0/+10
| | | | | | | | Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132322 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the dwarf numbers from the D registers. They don't have dwarf numbersRafael Espindola2011-05-291-16/+16
| | | | | | | | and should probably be encoded as DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132274 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some dwarf register numbers.Rafael Espindola2011-05-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132136 91177308-0d34-0410-b5e6-96231b3b80d8
* Increase number of available registers when target is MIPS32.Akira Hatanaka2011-05-191-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131660 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-11-17 18:06:19 +0000