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path: root/lib/Target/Mips/Mips64InstrInfo.td
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* [mips] Add definition of instruction "drotr32" (double rotate right plus 32).Akira Hatanaka2013-09-071-0/+1
* [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fitAkira Hatanaka2013-09-071-20/+14
* [mips] Set instruction itineraries of loads, stores and conditional moves.Akira Hatanaka2013-09-061-8/+8
* [mips] Clean up definitions of move word from/to coprocessor instructions.Akira Hatanaka2013-08-281-21/+9
* [mips] Remove predicates that were incorrectly or unnecessarily added.Akira Hatanaka2013-08-201-1/+1
* [mips] Resolve register classes dynamically using ptr_rc to reduce the number ofAkira Hatanaka2013-08-201-62/+34
* [mips] Rename HIRegs and LORegs.Akira Hatanaka2013-08-141-8/+8
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-081-8/+8
* [mips] Delete register class HWRegs64.Akira Hatanaka2013-08-081-1/+1
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-141/+141
* [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates ofAkira Hatanaka2013-08-061-13/+16
* [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'Akira Hatanaka2013-08-061-26/+5
* [mips] Replace usages of register classes with register operands. Also, removeAkira Hatanaka2013-08-061-45/+42
* [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,Akira Hatanaka2013-08-011-12/+6
* [mips] Rename instruction DANDi to ANDi64.Akira Hatanaka2013-07-311-4/+4
* [mips] Define instruction itineraries IIArith and IILogic.Akira Hatanaka2013-07-311-12/+16
* [mips] Use ADDu instead of OR to copy general purpose registers. Also, deleteAkira Hatanaka2013-07-221-3/+0
* [mips] Add instruction itinerary classes for mult, seb and slt instructions.Akira Hatanaka2013-07-121-4/+4
* [mips] Add new InstrItinClasses for move from/to coprocessor instructions andAkira Hatanaka2013-07-021-11/+11
* [mips] Add instruction selection patterns for blez and bgez.Akira Hatanaka2013-05-211-0/+5
* [mips] Trap on integer division by zero.Akira Hatanaka2013-05-201-2/+2
* Mips assembler: Add branch macro definitionsJack Carter2013-05-161-7/+13
* [mips] Fix handling of instructions which copy to/from accumulator registers.Akira Hatanaka2013-04-301-3/+1
* [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.Akira Hatanaka2013-03-301-4/+14
* [mips] Define pseudo instructions for spilling and copying accumulatorAkira Hatanaka2013-03-301-0/+8
* [Mips Assembler] Add support for OR macro with imediate opperandJack Carter2013-03-281-1/+3
* [Mips Assembler] Add alias definitions for jalJack Carter2013-03-281-0/+4
* [mips] Print move instructions.Akira Hatanaka2013-03-041-1/+1
* [mips] Add definition of JALR instruction which has two register operands. Ch...Akira Hatanaka2013-02-071-0/+3
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-051-13/+20
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-181-31/+29
* This patch tackles the problem of parsing Mips Jack Carter2013-01-121-49/+68
* Remove # from the beginning and end of def names. The # is a paste operator a...Craig Topper2013-01-071-8/+8
* [mips] 80 columns.Akira Hatanaka2013-01-041-4/+8
* [mips] Reorder template parameters. Remove class shift_rotate_imm32 andAkira Hatanaka2013-01-041-26/+26
* [mips] Refactor instructions which move data from or to coprocessors.Akira Hatanaka2013-01-041-16/+16
* [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardwareAkira Hatanaka2012-12-211-12/+13
* [mips] Refactor SYNC and multiply/divide instructions.Akira Hatanaka2012-12-211-10/+6
* [mips] Refactor jump, jump register, jump-and-link and nop instructions.Akira Hatanaka2012-12-211-3/+3
* [mips] Refactor load/store left/right and load-link and store-conditionalAkira Hatanaka2012-12-211-18/+15
* [mips] Refactor load/store instructions.Akira Hatanaka2012-12-211-11/+11
* [mips] Refactor LUI instruction.Akira Hatanaka2012-12-211-1/+1
* [mips] Refactor count leading zero or one instructions.Akira Hatanaka2012-12-211-2/+2
* [mips] Refactor sign-extension-in-register instructions.Akira Hatanaka2012-12-211-2/+2
* [mips] Refactor instructions which copy from and to HI/LO registers.Akira Hatanaka2012-12-211-4/+4
* [mips] Refactor logical NOR instructions.Akira Hatanaka2012-12-211-1/+1
* [mips] Refactor SLT (set on less than) instructions. Separate encodingAkira Hatanaka2012-12-201-4/+6
* [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass Akira Hatanaka2012-12-201-14/+14
* [mips] Refactor conditional branch instructions with one register operand.Akira Hatanaka2012-12-201-4/+4
* [mips] Refactor conditional branch instructions with two register operands.Akira Hatanaka2012-12-201-2/+2